New Cores Products

GPS RF Tuner IP Core is optimized for size, functionality.

With standard digital output and die area of 4 mm-², CI10084tg supports GNSS systems in L1 band and is also compatible with Galileo. It uses fractional PLL, letting designers leverage crystal frequencies available in host application, while options allow for parameter optimization. This integrated low-noise RF front-end for GPS receivers suits companies developing new GPS devices, adding GPS...

Processor Cores are fully synthesizable for flexibility.

As synthesizable version of IBM PowerPC 464 hard core, PowerPC 460S allows SoC designers to select L2 cache size, L1 cache size, and multi-core processor local bus necessary to optimize their design. This 32-bit embedded processor core also supports an optional floating point unit. As synthesizable version of 32-bit embedded IBM PowerPC 405 hard core, PowerPC 405S supports user-definable L1 cache...

Integrated Device facilitates SATA integration.

Used in solid state drives, HDDs, and optical disk drives, DesignWare-® SATA Device IP is comprised of Device, Host, PHY IP (90 or 65 nm process), and Verification IP. It passes SATA-IO Building Block interoperability testing and demonstrates full SATA functionality, helping designers reduce risk of integrating SATA interface into SoC designs. While supporting transfer speeds of 1.5 and 3.0...

HDMI® 1.3 PHY IP Core operates at up to 10.5 Gbps.

Produced in 90 nm CMOS technology, HD-PXL(TM)-1.3 transmitter IP core suits high-performance video interconnect applications. First version meets HD standards up to 2.25 Gbps, while second supports serial communications at speeds to 3.5 Gbps per channel for extended HD resolutions and backward compatibility to first version. Both support color depth of up to 16 bits and integrate feature set for...

Cold Forming: A Cost Effective Alternative to Machining Small Parts

Cold forming offers tight tolerances, dimensional stability, and advanced surface finishes, while also saving you in raw material wastes costs.

Low Power Processing Cores suit portable/embedded MCU market.

Including architectural clock gating and dynamic voltage and frequency scaling, ARC-® Energy PRO 32-bit configurable cores include ARC Energy PRO 20 and ARC Energy PRO 30 models. ARC Energy PRO 20 cacheless CPU/DSP core features closely coupled, single cycle memories that provide fast computation and deterministic response. ARC Energy PRO 30 CPU/DSP core functions as complete processor solution...

IP System includes PCI-SIG I/O virtualization technology.

Operating at 2.5 or 5.0 GT/s per lane, DesignWare-® IP for PCI Express supports multiple Physical Functions and Virtual Functions such as Alternative Routing ID Interpretation, Function Level Reset, and Address Translation Services. PCI-SIG I/O Virtualization technology, which builds on PCI Express protocol stack, minimizes system hardware requirements by enabling simultaneous sharing of...

Real-Time Operating System enhances DSP architectures.

Occupying as little as 8 KB of memory, OSEck (OSE Compact Kernel) is DSP-optimized RTOS that delivers preemptive, event-driven, real-time response and offers built-in error detection and handling. It is available in CEVA-TeakLite-III(TM) cores, which feature native 32-bit processing and dual Multiply-Accumulate (MAC) architecture. As scalable VLIW-SIMD DSP architecture with OSEck, multipurpose...

PHY IP promotes PCI Express interface integration.

DesignWare PHY IP for PCI Express 2.0 (Gen II) provides designers with complete, silicon-proven PCI Express 2.0 IP solution that includes digital controllers, PHY, and verification IP. Accessing all IP from one provider helps lower risk of integrating 5.0 Gbps PCI Express interface into SoC designs. Along with diagnostic capabilities and ATE test vectors for at-speed production testing of PHY,...

Integrated SoC Devices consume low power at 1 GHz speed.

Discovery(TM) Innovation Series is comprised of 3 devices - MV78200, MV78100, MV76100 - that integrate single- or dual-core, gigahertz-capable, ARM instruction set-compliant processors along with I/O peripherals. They support processor speeds from 800 MHz to 1.2 GHz and incorporate up to 512 KB L2 cache per core. Additional features include x4 PCI-Express(TM) interfaces, multiple USB 2.0 ports,...

USB PHY IP enables interoperability with USB 2.0 products.

Available in 45 nm process node, DesignWare USB 2.0 nanoPHY IP features built-in tuning circuits that enable post-silicon adjustments to account for unexpected chip/board parasitics or process variations without need to modify existing design. Unit is targeted for broad range of high-volume, mobile and consumer applications where key requirements include minimal area and low power consumption.

High or Low Volume Custom Crates and Boxes Available from Reid Packaging

Reid provides mil-spec crates and corrugated boxes in custom dimensions from single to triple wall and will even package them on-site. Check out the video to learn more.