Cores

MCU Core has synchronous RTL design.

Able to process one instruction cycle in single clock cycle, TLCS-870/C1 8-bit microcontroller (MCU) core suits applications from portable digital products to those requiring large capacity ROM. It supports up to 128 Kb of address space, attained with memory management method that manages code and data in separate areas. Binary compatible with previous Toshiba 8-bit MCUs, core allows existing...

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Programmable Baseband Processor targets multimode devices.

LeoCore-1 Programmable Baseband Processor SIP Core is based on SIMT (Single Instruction stream Multiple Tasks) architecture which allows parallel tasks to be controlled by single instruction flow. Architecture features programmable on-chip network integrated with hardware acceleration blocks. Suited for multimode, mobile, wireless communication, core supports WLAN standards 802.11 a/b/g,...

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Fujitsu Introduces Trio of New Macros for ASIC Designs for 90nm and 110nm

New PCI Express, 10G SerDes, Serial ATA Macros Support Server, Wireless, Storage and Desktop Computing Applications SUNNYVALE, Calif., Aug. 29 // -- Fujitsu Microelectronics America, Inc. (FMA) today expanded its portfolio of IP cores for networking, communications and storage system applications, introducing three new macros for custom ASIC designs. The new macros include Fujitsu's Serial ATA...

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Altera, Sarance Technologies and Cortina Systems Join Forces on First Interlaken Protocol IP Core for FPGAs

Targets High-Speed Networking and Storage Equipment, Demonstrates Stratix II GX FPGA Capability in 6.375-Gbps Applications San Jose and Sunnyvale, Calif., and Ottawa, Ontario, August 14, 2006- Altera Corporation (NASDAQ: ALTR), design services provider Sarance Technologies and communications semiconductor specialist Cortina Systems today announced the availability of the industry's first...

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Altera and Elektrobit Offer First OBSAI RP3-01 Development Kits for Wireless Base Station Designs

San Jose, Calif. and Oulunsalo, Finland, August 15, 2006-Altera Corporation (NASDAQ: ALTR) and Elektrobit Group Plc. (HEX:EBG1V) today announced the availability of the industry's first development kits for designing applications in compliance with the Open Base Station Architecture Initiative (OBSAI) Reference Point 3-01 (RP3-01) specification for remote RF heads. The kits include a Stratix-®...

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Chip Industry's Top Manufacturers License ARM Debug and Trace Technology

CAMBRIDGE, England, April 24/-- ARM Coresight Design Kits Are Available for Complete Mobile, Automotive and Consumer System-on-Chip Designs ARM (LSE:ARM ; Nasdaq:ARMHY) today announced that more than ten industry-leading semiconductor companies including Broadcom Corporation, Royal Philips Electronics and Samsung are integrating ARM(R) CoreSight(TM) debug and trace capabilities into their future...

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Network Security Solution promotes flexible topologies.

Comprised of Certicom MCE software module and Certicom ECC Core hardware IP core, Certicom Security for Sensor Networks secures low-power, wireless sensor networks and enables them to be scalable, mobile, and self-configurable. Product uses elliptic-curve cryptography to add provable identity to sensor devices, which provides security from design and development through to manufacturing,...

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Processor Core features integrated DSP functionality.

Eliminating need for separate DSP, MIPS32Â-® 24KE(TM) 32-bit processor cores deliver converged RISC/DSP functionality and can achieve clock frequency of 850 MHz. Fully static, fully synthesizable design requires no custom cells or memories, occupies as little as 2.0 mmÂ-², and consumes 0.43 mW/MHz. At 1.46 DMIPS/MHz, design provides 1,240 DMIPS, suitable for power-sensitive consumer...

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IP Core targets Xilinx Virtex and Spartan FPGAs.

Incorporating logical layer, transport layer, and physical layer, Serial RapidIO supports I/O and message passing. Compliant with Serial RapidIO specification 1.2, IP core suits wide range of applications for embedded, communications, wireless, storage, and defense markets. It can also be used to create multi-port switches to aggregate other Serial RapidIO inputs.

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IP Core suits embedded mixed-signal applications.

Offering Pulse Width Modulation IP building block for digital-to-analog conversion, CorePWM is optimized for non-volatile FPGAs. When implemented in Actel Fusion(TM) Programmable System Chip, CorePWM enables design of single-chip, closed-loop control system. Unit has register-based interface that can be used with or without microcontroller. It offers up to 8 PWM output channels with 8-bit PWM...

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