Cores

Interface IP suits DDR2 SDRAM subsystems.

DesignWareÂ-® DDR2 SDRAM system-level interface IP helps ensure overall memory system performance of up to 800 Mbps by delivering complete DDR2 SDRAM memory interface solution that includes scalable digital controller, complete integrated physical interface hard macro, and matching verification IP. Latter provides full support for VCSÂ-® Native Testbench. Solution is designed to operate...

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IP Bridge connects PCI Express to AMBA 2.0 AHB protocol.

DesignWareÂ-® Bridge to AMBA 2.0 AHB protocol is used in conjunction with DesignWare digital IP portfolio for PCI Express standard, including Endpoint, Root Complex, and Dual Mode Cores. DesignWare Bridge core enables designers of networking, embedded, storage, and computer applications to add PCI Express external connectivity to their SoCs in order to connect to available PCI Express...

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Processor Core is used for portable multimedia applications.

Compliant with CEVA-X Instruction Set Architecture, Model CEVA-X1641(TM) fully synthesizable core enables users to configure optimal memory size and structure for applications such as WiMAX and WiBro. Product offers 4 MAC units operating in parallel coupled with 128-bit data memory bandwidth. Digital signal processor (DSP) core features combined VLIW/SIMD architecture and incorporates video...

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MIPS Technologies Unveils New SOC-it-® Platform Strategy for MIPS-Based(TM) SoCs

MIPS-Verified(TM) Platform to Simplify Design of High-Performance SoCs and Accelerate Time-to-Market FALL PROCESSOR FORUM, SAN JOSE, Calif., Oct. 10 / With time-to-market pressures mounting for complex 90nm and 65nm SoC designs, MIPS Technologies, Inc. (NASDAQ:MIPS) today unveiled a new platform strategy for its entire range of MIPSÂ-® processors. The fully verified SOC-itÂ-® Platform and...

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Soft Processor boosts performance of 65 nm Virtex-5 FPGAs.

Operating at 210 MHz, MicroBlaze(TM) 5.00 32-bit RISC core delivers 240 DMIPS in Virtex(TM)-5 FPGAs and extends floating point performance to 50 MFLOPS. It includes configurable cache line size options of 4 or 8 words, instructions that are useful with data-intensive multimedia applications, and Processor Version Register that enables multi-processing applications. Processor's user selectable...

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Altera Nios II Embedded Processor Receives Electronic Engineering & Product World Award

San Jose, Calif., Oct. 24, 2006-Altera Corporation (NASDAQ: ALTR) announced today that its NiosÂ-® II family of embedded processors received the Electronic Engineering & Product World (EEPW) 2006 Editors' Choice Award for China's Best Embedded System Technology. The Nios II family was one of ten winners selected in a three-step voting process that included an online readers' survey and...

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Xilinx Strengthens Automotive Offering with Industry's Only Complete Programmable MOST-® Solution

Highly Integrated FPGA-Based MOST Network Interface Controller Solution Enables Flexible System Partitioning for Infotainment Applications SAN JOSE, Calif., Oct. 9 // -- Xilinx, Inc. (NASDAQ:XLNX) today announced its programmable solutions roadmap based on the Media Oriented System Transport (MOST) networking protocol for automotive electronics. Based on its market-leading programmable logic...

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Synopsys and ARM Announce Immediate Availability of CCS Noise Models for ARM Physical IP

Next-Generation Signal Integrity Sign-off Models to Deliver Improved Accuracy and Reduced Turnaround Time MOUNTAIN VIEW, Calif. and CAMBRIDGE, England, Oct. 4 // -- Synopsys, Inc. (NASDAQ:SNPS), a world leader in semiconductor design software and ARM [; (NASDAQ:ARMHY)], today announced that the ARMÂ-® Advantage(TM), Metro(TM) and SAGE-X(TM) standard cell libraries, part of its ArtisanÂ-®...

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DDR2 SDRAM Interface works with Stratix II FPGAs.

This 667 Mbps DDR2 SDRAM interface for StratixÂ-® II and Stratix II GX FPGAs combines auto-calibration DDR2 PHY and Northwest Logic's DDR2 SDRAM Controller Core. Former is supported by set of IP cores, demonstration boards, characterization reports, and simulation models, all designed to help engineers successfully interface AlteraÂ-® FPGAs to DDR2 SDRAM. DDR2 SDRAM Controller Core...

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Esmertec and MIPS Technologies Announce Optimal Java(TM) Solution on MIPS32-® 24Kc(TM) Processor for Blu-ray Disc(TM) Products

Market leader Pioneer Selected High-Performance Solution for its Blu-ray Disc(TM) Players DUEBENDORF-ZURICH, Switzerland and MOUNTAIN VIEW, Calif., Sept. 26 -- Esmertec(TM) , and MIPS Technologies (NASDAQ:MIPS) today announced the availability of an optimal high-performance Java(TM) solution for Blu-ray Disc(TM) (BD) players. Pioneer Corporation, a leading manufacturer of consumer and business...

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