Cores

DSP IP Core is suited for LTE and 4G SOC designs.

ConnX Baseband Engine provides computational throughput of 16 x 18-bit MACs/cycle, with application-specific instruction set optimized for LTE and 4G wireless base stations. It is also suitable for multimode, multistandard terminal devices as well as components for wireless handsets.

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DSP Core targets wireless handsets and base stations.

Offering computational throughput of 16 18-bit MACs per cycle, ConnX Baseband Engine enables baseband processing for 3G, LTE, and 4G wireless equipment. Unit offers automatic vectorization for ANSI C programs and optimized instructions for FFT, FIR filters, and complex matrix operations. Designed for 8-way SIMD and 3-way VLIW, engine has 160-byte vector register files supporting 20bx8 and 40bx4...

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Desing Platform Kits accelerate development of SoCs.

Designed to help shorten development cycles, Xilinx Base Targeted Design Platform Kits combine v11.2 release of ISE-® Design Suite, IP, and pre-verified reference designs targeting Virtex-6 or Spartan-6 FPGAs. Reference designs outline best practices for integrating custom elements into base design and implementing features such as DDR2 and DDR3 memory interfaces, high-speed serial I/O, and...

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IP Core aids wireless basestation, remote radio head design.

Supporting channel speeds to 6.144 Gbps, Common Public Radio Interface (CPRI) v4.1 supports LTE and WiMAX standards as well as legacy WCDMA, CDMA, and other air-interface standards. Developers gain configurable solution that complements Altera 40 nm FPGAs for up to 3.072G CPRI line rates as well as Stratix-® IV GX FPGAs and HardCopy-® IV ASIC solutions for up to 6.144G CPRI line rates. IP core...

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IP Components slash power in datapath circuits.

Intended for wireless, networking, and DSP companies, DesignWare minPower Components offer power-optimized datapath architectures that enable DC Ultra(TM) synthesis tool to automatically generate circuits that suppress switching activity and glitches, reducing dynamic and leakage power for mobile devices. In addition to automatically inferable components, minPower Components include instantiable...

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Controller IP Cores target next-generation chip designs.

Based on preliminary version of PCI Express-® 3.0 specification, Databahn(TM) Controller IP Cores accelerate overall deployment of PCIe 3.0 technology into storage and networking systems. Preliminary PCIe 3.0 specification increases PCIe 2.0 interconnect bandwidth from 5 GT/s to 8 GT/s. Cores support TLP Prefix, Atomic Operations, Resizable BARS, and Alternative Routing-ID, as well as scalable...

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HDMI 1.3 Receiver Interface enhances digital home solutions.

Based on 90 nm technology, 45 nm HDMI 1.3 receiver IP solution is comprised of HDMI RX controller and HDMI RX PHY. Controller features video interface flexibility, supporting all CEA-861D video formats, and also supports True Color and Deep Color modes and several video pixel encodings as well as Gamut Metadata. Capable of supporting cables up to 20 m, HDMI 1.3 RX PHY features automatic adaptive...

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Interface IP drives HDMI integration in portable devices.

Optimized for SoC integration, 40 nm HDMI 1.3 Interface IP (Controller + PHY) offers analog programmability and ability to implement subset of HDMI 1.3 specification that let designers select specific features needed for their application to further reduce area and power. HDMI 1.3 Tx Interface in TSMC 40 nm supports video modes compliant to CEA-861-D as well as I2S and S/PDIF digital audio...

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Programmable DSP Core targets wireless communications.

Incorporating up to 4 Vector Units into CEVA-X framework to deliver up to 200 billion operations/sec, CEVA-XC(TM) supports full transceiver processing for multiple air interfaces in software, including 4G mobile standards; LTE class 5 and WiMAX II, as well as 3G, 3.5G, Wi-Fi, GPS, and MobileTV. Core integrates Power Scaling Unit, supporting multiple clock and voltage domains and low power...

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Host Controller supports SDIO Specification 2.0.

Available as single IP core, SDIO-HOST is suited for any memory card or SDIO application. Support for CPRM mechanism is realized through implementation of Cryptomeria cipher algorithm for symmetric data encryption. With set of wrappers for AMBA-® AHB, APB, Avalon, and Wishbone, core can be reused in different design environment within one multiuse license. Support for MMC 4.2 guarantees...

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