Cores

Public Key Hardware Accelerator enhances embedded security.

Public Key Crypto Engine BA414E exploits potential hardware parallelism to optimize performance and area in any configuration. With re-configurable elementary DSP blocks, it can be mapped to any existing FPGA technology as well as all ASIC processes. Product has just less than 30k ASIC gates and, by stretching hardware same core, can execute 5,000+ operations per second for 1,024-bit CRT sign or...

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Data Converter IP Solutions leverage 65 nm LL process technology.

DesignWare(TM) Data Converter IP solutions, intended for SMIC's 65 nm Low Leakage (LL) process technology, help designers improve chip power efficiency and integration in battery-powered broadband wireless communications and DTV reception applications. Products include 10-bit, 80 MSPS dual pipeline ADC; 10-/8-bit, 2 MSPS SAR ADC with differential 8:1 input mux; 12-bit, 160 MSPS Current Steering...

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Qualcomm Announces Quad-Core Snapdragon for Next Generation Tablets and Computing Devices

--New Chipset Includes Next Generation CPU Architecture with Quad-Core and Adreno GPU-- BARCELONA, Spain -- Qualcomm Incorporated (Nasdaq: QCOM) today announced its quad-core Snapdragon(TM) chipset designed to meet the requirements of next generation tablets and computing devices. The new quad-core APQ8064(TM) is the flagship chipset in the new family of Snapdragon chipsets and is based on the...

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IP Engines network Sony block cameras.

IP Engines network Sony block cameras.

With Pleora iPORT(TM) SB-Pro IP Engines, users can transform Sony block cameras into GigE Vision compliant cameras. Units abstract Sony VISCA protocol into industry-standard GenICam interface over Ethernet. Available as OEM board sets designed for use in variety of housings, IP engines transmit video at up to 1080i resolution and up to 30 frames/sec with low latency. Applications include military...

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CEVA and mimoOn Offer Complete LTE PHY Reference Architectures for UE and eNodeB Applications

LTE reference architectures lower overall cost and accelerate time-to-market for semiconductor vendors and OEMs MOUNTAIN VIEW, Calif. -- CEVA, Inc. [(Nasdaq: CEVA); (LSE: CVA)], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, and mimoOn, the leading licensor in LTE software implementation for programmable radio platforms, announced today a range of...

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Now That's Performance - Texas Instruments' C66x Core Surpasses All Other DSPs in the Market

Independent BDTI benchmarks show TI's C66x DSP core delivering the industry's top results on fixed- and floating-point performance BARCELONA, Spain -- MOBILE WORLD CONGRESS -- Continuing to lead the industry with the highest performing digital signal processors (DSPs), Texas Instruments Incorporated (TI) (NYSE: TXN) today announced a greater performance achievement with its TMS320C66x DSP core,...

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Direct Chip-to-Chip Interconnect offers USB 2.0 performance.

High Speed Inter-Chip (HSIC) compatible PHY IP enables low-power USB 2.0 chip-to-chip connections. It allows OEMs to set up direct connection on PCB between USB host chip and other on-board USB devices. Implementing 240 MHz DDR interface, HSIC product supports 480 Mbps data transfer of USB protocol, minimizes required board space, and is USB software compatible.

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CEVA to Showcase Next-Generation 4G and Multimedia Technologies at Mobile World Congress

LTE, 3D video, gesture recognition and mobile audio and voice technologies on display from the world's #1 licensor of DSP cores and platforms; Visit CEVA in Stand 1F33, Hall 1 at Mobile World Congress 2011 MOUNTAIN VIEW, Calif. - CEVA, Inc. (Nasdaq: CEVA); (LSE: CVA), the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores for the mobile handset, portable and...

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LTE Evolved Packet Core advances smart mobile Internet.

Based on Tellabs® SmartCore® 9100 platform, Long Term Evolution Evolved Packet Core can enable greenfield operators to build next-generation network with compact footprint for distributed network design and advanced content awareness. With integrated deep packet inspection, granular QoS, and traffic management architecture, SmartCore 9100 enables operators to monitor real-time traffic, enforce...

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Main Profile Video Encoder Core leverages H.264 tools.

Optimized for video output quality and application support, H264-MP-E enables Full HD, 1920 x 1080p, 30 fps video in FPGAs and beyond 1920 x 1080p at 60 fps in ASICs. Hardware systems integration is facilitated by flexible, streaming-capable interfaces; stand-alone, processor-free operation; and low-bandwidth, latency-tolerant, external memory interface. Also, run-time tunable parameters and...

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