Cores

Altera Highlights Its FPGA-Acceleration Technology for Software Programmers at SuperComputing 2014

Altera Showcasing the Industry's Only FPGAs with Integrated Floating Point DSP Blocks Capable of Delivering up to 1.5 TFLOPS in a Single Chip SAN JOSE, Calif. –- Altera Corporation (NASDAQ: ALTR) will demonstrate its FPGA-based acceleration technologies to system designers and software programmers at SuperComputing 2014 (SC14). Altera's participation at SC14 includes several demonstrations...

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Altera and IBM Unveil FPGA-accelerated POWER Systems with Coherent Shared Memory

POWER8 Systems that Leverage Reprogrammable FPGA Accelerators Gain Significant Improvements in System Performance, Efficiency and Flexibility NEW ORLEANS- — SuperComputing 2014 - Altera Corporation (Nasdaq: ALTR) and IBM (NYSE: IBM) today unveiled the industry's first FPGA-based acceleration platform that coherently connects an FPGA to a POWER8 CPU leveraging IBM's Coherent Accelerator...

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Altera and IBM Unveil FPGA-accelerated Systems Coherently Attached to POWER CPU

OpenCL-Enabled Acceleration Platform Leverages CAPI to Coherently Share Memory between an FPGA Accelerator and POWER8 CPU SuperComputing 2014, New Orleans, LA – Altera Corporation (Nasdaq: ALTR) and IBM (NYSE: IBM) today unveiled the industry's first FPGA-based acceleration platform that coherently connects an FPGA to a POWER8 CPU leveraging IBM's Coherent Accelerator Processor Interface...

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Xilinx Demonstrates All Programmable Solutions for Industrial Automation Applications at SPS/IPC/Drives 2014

All Programmable FPGAs and SoCs enable differentiated, highly integrated, and system cost optimized solutions for Industry 4.0 applications SAN JOSE, Calif. - Xilinx, Inc. (NASDAQ: XLNX) will demonstrate All Programmable solutions for industrial automation applications at SPS/IPC/Drives 2014.-  Xilinx, systems companies and ecosystem partners will demonstrate how Xilinx All Programmable FPGAs...

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Xilinx Announces Industry's First Low Latency 25G Ethernet IP for FPGAs to Address Throughput Challenges in Data Center Applications

Company demonstrates new 25G Ethernet MAC and PCS LogiCORE IP at Supercomputing 2014 SAN JOSE, Calif.- – Xilinx, Inc. (NASDAQ: XLNX) today announced the industry's first low latency 25G Ethernet IP for FPGAs to address throughput challenges in data center applications. The low latency 25G Ethernet MAC and PCS LogiCORE™ IP solution helps to reduce data center CapEx by providing a migration...

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TI Makes Programming in Real Time as Easy as 1-2-3

Introducing expanded PRU software support and the first PRU cape plug-in board for BeagleBone Black from TI DALLAS- – The programmable real-time unit (PRU) on Sitara™ processors from Texas Instruments (TI) (NASDAQ: TXN) enables customers to differentiate their products by offloading real-time processing from the ARM® core. The PRU is a 200MHz low-latency multicore co-processor optimized for...

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Easy Testing and Programming of Texas Instruments TM4Cxx Microcontrollers with VarioTAP®

Universal processor emulation with VarioTAP® technology by GOEPEL electronics is now available for the Tiva™ C series from Texas Instruments. The processor is reconfigured to provide design-integrated test and programming instruments via the native debug port. A respective VarioTAP® model, as part of an extensive IP library, contains all relevant access information for the respective target...

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Verification IP supports all popular 3D memory standards.

Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory...

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Low-Power IP Core targets multi-core implementations.

Low-Power IP Core targets multi-core implementations.

Based on Cortus v2 instruction set, Model APS25 supports accelerating computation through using coprocessors or symmetric multiprocessing and can serve as building block in dual- or multi-core systems. Cortus v2 instruction set allows seamless mixing of 16-, 24-, and 32-bit instructions without mode switching. Featuring Harvard architecture, core provides sixteen 32-bit registers, 5-stage...

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Low-Power IP Core targets Internet of Things applications.

Low-Power IP Core targets Internet of Things applications.

Based on Cortus v2 instruction set, Model APS23 is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart. Cortus v2 instruction set allows seamless mixing of 16-, 24-, and 32-bit instructions without mode switching. Featuring Harvard architecture, core has sixteen 32-bit registers, 3-stage pipeline, and sequential multiplier....

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