New NAND Flash Controller from Arasan is Compatible with ONFI 4.0 and 3.2 Specifications
Ideal for UMC 28nm SoC Designs and can be integrated with proprietary NAND flash controllers through a simplified version of the standard DDR DFI Interface. PHY IP DFE contains data buffering FIFO and ONFI I/O data synchronizing Flops, DLL clocks phase selection logic and BIST . PHY AFE contains ONFI 4.1 IO PADS, retention mode, analog DLL and DLL clock frequency .
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New RXv3 32-Bit CPU Core Comes with Enhanced RX Core Five-Stage Superscalar Architecture
The Renesas’ RXv3 32-bit RX CPU Core is designed for use in RX microcontroller used in motor control and industrial applications. The core boosts RX CPU core architecture with up to 5.8 CoreMark®/MHz. It enables the RX600 MCU to achieve 44.8 CoreMark/mA that reduces access time and power consumption during on-chip flash memory reads. The RXv3 unit uses a save register bank with up to 256 banks...
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Micrometal Offers EQ Distributed Gap Cores for Surface Mount Applications
The EQ Series Distributed Gap Cores are available in six geometries ranging from 20 mm to 50 mm. They are offered in Sendust (MS), Hi-Flux™ (HF) and FluxSan™ formulations with 26, 40 or 60 permeability values. The unit’s distributed gap nature allows them to be used with little or no center-leg gap that reduces losses related with fringing flux at higher frequency. The cores are suitable...
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Arasan Presents MIPI C-PHY/ D-PHY Combo IP Core for Mobile and Automobile SoCs
The MIPI C-PHY / D-PHY Combo IP Core is available for 65 nm to 12 nm process nodes and is compliant to C-PHY specification Version 1.2 and D-PHY 1.2 specifications. The unit is designed for camera sensor applications and allows customers to implement C-PHY with less impact area.
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Reflective Tapes and Their Visibility Control Applications
This ebook provides an overview into reflective tapes and their visibility control applications.
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eSilicon Licenses Industry-Leading SiFive E2 Core IP for Next-Generation SerDes IP
Configurability of industry's lowest-area, lowest-power core provided optimal solution for eSilicon SAN MATEO, Calif. and SAN JOSE, Calif., Aug. 7, 2018 /PRNewswire/ -- SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after...
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New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X
VDC-M Encoder and Decoder IP Cores are designed for mobile phones, tablets, and AR/VR products and can be adopted in to MIPI Display Serial Interface℠ 2 v1.1 standards. Units support all VDC-M encoding/decoding mechanisms and use few transmission lanes compared to DSC. The cores offer a bitstream as low as 6 bits per pixel for HDR content and support up to ESA display compression-M standards.
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Medeco B Interchangeable Core uses unpatented SFIC keyways.
Medeco B Small Format Interchangeable Core is available in 1C, 1D, AB, BB, CB, DB, EB, FB, GB, HB, JB, KB, LB, MB, QB, RB, TA, TB, TC, TD, TE, WA, WB, WC, WG, WH & WY standard keyways. Unit is offered in 6 and 7 pin format and 14 architectural finishes. Product features reinforced sleeve design.
Read More »IntelliProp Announces Gen-Z Persistent Memory Controller Combining DRAM and NAND
Visit us at Flash Memory Summit - August 8-10, 2017 and see our demos LONGMONT, Colo., Aug. 8, 2017 - IntelliProp, Inc., a leader in innovative Intellectual Property (IP) Cores and semiconductors for Data Storage and Memory applications, announced today the IPA-PM185-CT, Gen-Z Persistent Memory Controller, code named Cobra. This controller combines DRAM and NAND and sits on the Gen-Z fabric, not...
Read More »CAST Drives Automotive IP Forward with New AVB/TSN Ethernet and SAE J2716 Sensor Bus Cores Plus CAN-FD Time-Stamping
New IEEE 802.1AS AVB/TSN and SENT/SAE J2716 Cores now available; CAN/CAN-FD Controller Core now supports AUTOSAR-compliant time-stamping WOODCLIFF LAKE, N.J., June 13, 2017 - Semiconductor intellectual property provider CAST, Inc. today announced three significant improvements to its automotive IP family: A new IEEE 802.1AS Hardware Protocol Stack Core works with any eMAC (Ethernet Media Access...
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Embedded FPGA IP Core for TSMC 16FF+ and 16FFC with reconfigurable RTL.
Performing wide, single-stage logic around 1GHz at worst case PVT conditions, Embedded FPGA IP core for TSMC 16FF+ and 16FFC can be custom-designed for networking, base station and data center. Optimizing high speed control logic with single stage RTL logic, EFLX-100 can be built up from 100 LUTs to 3000 LUTs. Featuring 224 I/O, 6 Input LUTs with core area of 0.05mm2 , unit requires only 5...
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Vector® Sports Training Ball Offers Visible Point of Contact
Our goal is to help every athlete derive maximum enjoyment from their sport and become a better player. We offer a line of innovative training tools that combine cutting-edge technology and out of the box thinking to deliver an unbeatable competitive advantage. The Vector® Sports Training Ball is just another example of our commitment to innovation. To learn how the Vector® is helping ballplayers everywhere, see our video.
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