Synopsys, Inc.
Mountain View, CA 94043
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Software provides IC yield management.
Establishing connectivity between design, simulation, manufacturing, and test domains, Yield Explorer expedites discovery and mitigation of yield limiters in ICs. Program minimizes design re-spin through rapid and comprehensive capture of design-process-test interactions causing low yield. In addition to analytical functions, users benefit from Tcl scripting environment built into GUI, which...
Read More »EDA Software optimizes computer chip production process.
Lynx Design System uses RTL-to-GDSII design flow with methodologies required for implementing 65 and 40 nm designs with low-power techniques such as MCMM, SRPG, and DVFS. Foundry-Ready System accelerates chip implementation by prevalidating technology files and libraries. Configuration and execution of design flow is automated by Runtime Manager GUI while Management Cockpit offers browser-based...
Read More »STA Software has quad-core licensing as standard feature.
PrimeTime-® STA suite v2008.12 includes multicore processing technology that makes effective use of both single-core and multicore CPUs across compute server farms. It features runtime optimizations, allowing design engineers to run full timing and SI analysis on their large designs, early in implementation process. Software's multicore capability works seamlessly with job scheduling systems...
Read More »Service verifies PCB signal integrity.
DesignWare-® DDR PHY signal integrity service utilizes HSPICE-® circuit simulator's signal integrity simulation and delivers integrity analysis as detailed report, which analyzes DDR3/2 memory subsystem timing budget of PCBs. Report identifies sources of system errors before prototypes of chip, package, and PCB are manufactured. Also, DesignWare DDR3/2 IP built-in data training circuits enable...
Read More »Ethernet IP Solution offers precision clock synch.
DesignWare-® Ethernet MAC 10/100/1G IP includes support for IEEE 1588 specification, which provides standard method to synchronize devices on network with sub-microsecond precision. This capability is key requirement for consumer products in digital home applications as well as measurement and control systems. Interface to ARM-® AMBA-® 3 AXI(TM) protocol, also included, enables designers to...
Read More »FPGA Prototyping Board adopts Altera device and PCIe format.
Targeting algorithmic design and software development, HAPS(TM)-A31 single-Altera-® Stratix-® III SL340 FPGA prototyping board has PCIe form factor. It can be plugged directly into any 4-lane PCIe slot, and interface enables designers to tightly couple application software development to DSP algorithms and IP blocks as well as take advantage of Confirma(TM) ASIC/ASSP Rapid Prototyping Platform....
Read More »Software facilitates chip verification productivity.
VMM verification methodology lets chip developers use SystemVerilog to create verification environments using transaction-level, coverage-driven, constrained-random, and assertion-based techniques. In addition to multi-stream scenario generator, transactor iterator, and command-line options manager, solution incorporates Performance Analyzer application for analysis of shared design resources....
Read More »PHY IP helps integrate SATA interfaces into SoCs.
Silicon-proven DesignWare SATA PHY IP is designed for SMIC 130 nm process technology, for use in host and device applications such as mobile internet devices, set-top boxes, solid state drives, and optical disk drives. It consists of AHCI host and device digital controllers, as well as verification IP, and features built-in diagnostic capabilities and ATE test vectors. Relying on standard digital...
Read More »EDA Software accelerates design closure.
Featuring optimized runtimes, IC Compiler 2008.09 accelerates design closure through technology such as timing, variation-aware clock-tree synthesis with low-power techniques, DFM capabilities, and signoff-quality incremental design-rule checking. Acceleration is also attributed to technologies such as placement optimization, signal-integrity closure and hold-time fixing, multi-corner/multi-mode...
Read More »EDA Software speeds full-chip verification.
Added features to IC Compiler include incremental signoff-quality Design Rule Checking (DRC) and metal fill capability, enabling users to perform signoff-quality checks incrementally by calling Hercules from inside implementation environment. Technology to guard against corner-case DRC violations is also included. Pushbutton capability, powered by Hercules DRC/LVS, enables place-and-route...
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