Synopsys, Inc.
Mountain View, CA 94043
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Data Converter IP Products suit broadband communication SoCs.
DesignWare-® Data Converter IP solutions include 10- and 12-bit pipeline A/D converters running up to 250 MS/sec, as well as 14-bit current steering D/A converters running up to 400 MS/sec. Both are available in single-channel and dual-channel configurations. Able to process signal bandwidth beyond 100 MHz, units integrate into broadband wireless and wireline communication SoCs and suit WiFi,...
Read More »EDA Software speeds multicorner/multimode designs.
With In-Design technology, IC Compiler 2010.03 enables signoff-accurate static timing analysis, rail analysis, and physical verification during design. Software provides production support for all 28/32-nm design rules for major foundries. It includes pre-route feasibility engines, leakage optimization engine capable of handling more than 20 leakage variants, and ability to generate interactive...
Read More »MIPI 4G DigRF-Compliant IP accelerates LTE/WiMAX SoC development.
DesignWare-® MIPI-® 4G DigRF(SM) Master Controller IP enables designers to lower risk of integrating DigRF interfaces into baseband ICs and application processors accelerating time-to-market of LTE and Mobile WiMAX SoCs. Compliant to MIPI DigRF v4 1.00 specification, controller implements features defined for protocol and PHY adaptation layers. Configurability of IP RTL provides flexibility for...
Read More »Universal DDR Controllers support 2,133 Mbps performance rate.
Supporting DDR2, DDR3, Mobile DDR, and LPDDR2 SDRAM standards, DesignWare-® Universal DDR Protocol and Memory Controllers enable integration of multiple DDR interfaces into one design servicing range of products. Controller accepts memory access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to controller clock....
Read More »Rapid Prototyping Systems support SoC designand verification.
Featuring pretested DesignWare-® IP and advanced verification modes with Confirma software suite, HAPS-®-60 series systems allow users to write, execute, and debug code in near real-time system-level environment. Units achieve clock frequencies of up to 200 MHz and single HAPS board can support designs of up to 18 million ASIC gates. Verification modes include co-simulation through PLI and...
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MultiPHY IP supports 6 DDR standards.
DesignWare(TM) DDR multiPHY supports range of DDR SDRAM standards - LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), DDR2 - in single PHY. This lets designers target different DDR types for single chip through software control, promoting flexible integration into various applications. Supporting data rates from 0-1,066 Mbps, product offers DFI 2.1-compliant interface to memory...
Read More »EDA Software accelerates analog/mixed-signal engineering.
Galaxy Custom Designer(TM) incorporates SmartDRD design-rules-driven technology, which enables layout engineers to achieve design-rule-check (DRC) clean designs with reduced effort via automated repair tasks. Comprised of DRDAutoFix and DRDVisual, SmartDRD technology assists layout engineers during manual placement and routing by automatically bringing edited design into rule compliance....
Read More »DSP Development Software offers matrix data-type support.
System Studio C/C++ model-based analysis and simulation environment features matrix and vector data-type support that reduces coding and debugging effort for DSP simulation. Parallelized matrix and vector function libraries are optimized for multicore systems, and 2D and 3D visualization allows intuitive representation of matrix data. Model library includes implementations of functions such as...
Read More »EDA Software offers RTL synthesis solution.
Extending topographical technology, Design Compiler-® 2010 produces physical guidance to IC Compiler place-and-route solution, tightening timing and area correlation while speeding IC Compiler's placement phase. Program provides RTL designers access to IC Compiler's floorplanning capabilities from within synthesis environment, enabling what-if floorplan exploration. With scalable infrastructure...
Read More »Service verifies PCB signal integrity.
DesignWare-® DDR PHY signal integrity service utilizes HSPICE-® circuit simulator's signal integrity simulation and delivers integrity analysis as detailed report, which analyzes DDR3/2 memory subsystem timing budget of PCBs. Report identifies sources of system errors before prototypes of chip, package, and PCB are manufactured. Also, DesignWare DDR3/2 IP built-in data training circuits enable...
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