Synopsys, Inc.
Mountain View, CA 94043
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New JEDEC DDR5 Verification IP Uses Next-generation Native SystemVerilog UVM Architecture
Enables design and verification of next-generation memory devices with ease-of-use, fast integration and optimum performance, resulting in accelerated verification closure. Operates at up to 6400 Mb/s support key features of DDR5 standard including device size, burst length, DIMM topologies and RAS features. Ideal for broad range of enterprise applications including cloud, IoT, high-performance...
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New JEDEC DDR5 Verification IP Uses Next-generation Native SystemVerilog UVM Architecture
Enables design and verification of next-generation memory devices with ease-of-use, fast integration and optimum performance, resulting in accelerated verification closure. Operates at up to 6400 Mb/s support key features of DDR5 standard including device size, burst length, DIMM topologies and RAS features. Ideal for broad range of enterprise applications including cloud, IoT, high-performance...
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New Design and Visualization Workflow Solution Features Photorealistic Renderings
LucidShape CAA V5 enable designers to conceptualize and design automotive lighting products as well as generates physics-based photorealistic images. Help designers to create light guide designs fast, optimize light distributions and uniformity and achieve good as-built performance. Allow users to construct and simulate design variations fast as well as streamlines the creation of multiple design...
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New Design and Visualization Workflow Solution Features Photorealistic Renderings
LucidShape CAA V5 enable designers to conceptualize and design automotive lighting products as well as generates physics-based photorealistic images. Help designers to create light guide designs fast, optimize light distributions and uniformity and achieve good as-built performance. Allow users to construct and simulate design variations fast as well as streamlines the creation of multiple design...
Read More »New DesignWare USB4 IP Solution Operates at up to 40 Gbps
Supports multiple high-speed interface protocols including USB4, displayPort 1.4a TX, PCI express and thunderbolt 3 for efficient data transfer and simultaneous delivery of data, power and high-resolution video. Designed to meet functionality, power and area requirements of a broad range of storage, PC and tablet SoC designs as well as software development debug. USB4 PHY IP offers a high...
Read More »New DesignWare USB4 IP Solution Operates at up to 40 Gbps
Supports multiple high-speed interface protocols including USB4, displayPort 1.4a TX, PCI express and thunderbolt 3 for efficient data transfer and simultaneous delivery of data, power and high-resolution video. Designed to meet functionality, power and area requirements of a broad range of storage, PC and tablet SoC designs as well as software development debug. USB4 PHY IP offers a high...
Read More »Synopsys Announces Support of TensorFlow Lite for Microcontrollers on Energy-efficient ARC EM and ARC HS Processor IP
Highlights: The TensorFlow Lite for Microcontrollers port to the Synopsys DSP-enhanced DesignWare ARC EM and HS processors enables a wide range of machine learning applications on resource-constrained edge devices New memory-efficient framework with optimized embARC Machine Learning Inference library boosts neural network software performance by more than 5X Mountain View, Calif., May 27, 2020...
Read More »Synopsys Announces Support of TensorFlow Lite for Microcontrollers on Energy-efficient ARC EM and ARC HS Processor IP
Highlights: The TensorFlow Lite for Microcontrollers port to the Synopsys DSP-enhanced DesignWare ARC EM and HS processors enables a wide range of machine learning applications on resource-constrained edge devices New memory-efficient framework with optimized embARC Machine Learning Inference library boosts neural network software performance by more than 5X Mountain View, Calif., May 27, 2020...
Read More »New DesignWare IP Portfolio Enables High Data Rates
Enable designers to achieve aggressive performance, power and density requirements of their designs, while lowering integration risk. Help designers to incorporate necessary functionality into their designs while benefiting from the significant power and performance boost of our 5nm process technology. Ideal for DDR5, LPDDR5 and HBM2/2E delivers maximum memory bandwidth and power efficiency.
Read More »New DesignWare IP Portfolio Enables High Data Rates
Enable designers to achieve aggressive performance, power and density requirements of their designs, while lowering integration risk. Help designers to incorporate necessary functionality into their designs while benefiting from the significant power and performance boost of our 5nm process technology. Ideal for DDR5, LPDDR5 and HBM2/2E delivers maximum memory bandwidth and power efficiency.
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