Synopsys, Inc.
Mountain View, CA 94043
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Latest CODE V 11.3 Optical Design Software Comes with CAD Model Support
Offers two freeform surface shapes: Q2D Freeform Asphere and Extended Fringe Zernike. Features SpecBuilder that helps designers track and communicate whether project specifications and goals meet optical system designs. Extends optical engineering leadership with enhanced optomechanical product design and visualization.
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Calterah Semiconductor's Automotive Radar SoC Enters Mass Production Using Synopsys DesignWare ARC Processor IP
ISO 26262 ASIL Compliant ARC EM Processor IP Enables Calterah to Accelerate Safety Certification for Next-Generation Millimeter Wave Radar Chip MOUNTAIN VIEW, California and SHANGHAI, Dec. 12, 2019 /PRNewswire/ -- Highlights Calterah's new Alps chip series includes four transmitter channels at most, four receiver channels, a highly configurable waveform generator, and an integrated...
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Synopsys and TSMC Collaborate for Certification on 5nm Process Technologies to Address Next-Generation HPC, Mobile Design Requirements
Enhancements in Design and Verification Tools Target Gains in Performance and Ultra-low Power MOUNTAIN VIEW, California, Nov. 25, 2019 /PRNewswire/ -- Highlights: Tools certified for the latest version of TSMC's N5/N5P DRM and SPICE model Synopsys power optimization enabled to support ultra-low power requirement of mobile devices Implementation vs. signoff correlation, certified for timing and...
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New VC LP Solution for Low-power Signoff and Static Verification
Includes SAM based methodology, which enabled to achieve up to 5X performance gains and up to 6X less memory footprint with the same QoR. Contains machine learning-enabled analysis technology for improved QoR and high debugability. Reduces the overall turnaround time for verification signoff to ensure that subtle bugs do not escape into silicon.
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Synopsys DesignWare ARC Data Fusion IP Subsystem Incorporated by Himax in Their Artificial Intelligence WiseEye ASIC
Always-On Sensing ASIC Enables Machine Learning for Ultra-Low Power Applications MOUNTAIN VIEW, Calif., Nov. 12, 2019 /PRNewswire/ -- Highlights: Himax WiseEye ASIC platform is optimized for application developers deploying machine learning on battery-powered AIoT devices Synopsys DesignWare ARC Data Fusion IP Subsystem with audio software library, tightly coupled pulse density modulation...
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New TestMAX XLBIST Solution Provide Dynamic In-system Testing for Critical Failures
Delivers high fault coverage and shorter test time by overcoming silicon issues that impede self-test solutions. Enables design teams to minimize implementation turnaround time. Avoids issues such as iterative design modifications and significant silicon area increases and prolonged schedules that are common to previous in-system test technologies.
Read More »New Die-to-Die PHY IP Supports NRZ and PAM-4 Signaling from 2.5G to 112G Data Rates
Delivers maximum throughput per die edge for large MCM designs. Allows for partitioning of large dies into small dies while offering trade-offs for power, bandwidth per beachfront, latency and reach. Provides less than one picojoule per bit for ultra-low-power die-to-die and die-to-optical engine connectivity.
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Synopsys Ships More Than 3,000 HAPS-80 Prototyping Systems
HAPS-80's High Performance and Cost Effectiveness Has Driven Adoption by More Than 100 Companies MOUNTAIN VIEW, Calif., Oct. 29, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that it has shipped more than 3,000 HAPS®-80 prototyping systems since its introduction. HAPS-80 is deployed at more than 100 companies worldwide, including nine of the top 10 semiconductor...
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New ARC VPX DSP Processor IP Can Deliver 512 FLOPs and 32 Math Operations Per Cycle
Supports single-, dual-, and quad-core configurations and contains scalar execution unit and multiple vector computation units that support 8-bit, 16-bit, and 32-bit SIMD computations. Incorporates ultra-wide vector architecture to accelerate highly parallel automotive, sensor fusion, and communications applications. Offers ARC MetaWare development toolkit with C/C++ compiler and associated...
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Synopsys Design Platforms Enabled for Samsung Foundry 2.5D-IC Multi-Die Integration
Synopsys and Samsung Foundry Collaboration Delivers Customized Solution to Support 5G, AI, and HPC Applications MOUNTAIN VIEW, Calif., Oct. 17, 2019 /PRNewswire/ -- Highlights: Synopsys Fusion Design Platform and Custom Design Platform support 7LPP SoCs and SUB20LPIN silicon interposer Immediate foundry customer deployment through Samsung customized design flow Synopsys, Inc. (Nasdaq: SNPS)...
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