Synopsys, Inc.

FABU Technology Selects Synopsys' DesignWare IP Portfolio to Deliver Intelligence in ADAS and Autonomous Driving SoCs
Software

FABU Technology Selects Synopsys' DesignWare IP Portfolio to Deliver Intelligence in ADAS and Autonomous Driving SoCs

Portfolio of Silicon-Proven IP Meets Artificial Intelligence Processing, Memory, Connectivity, and Security Requirements while Accelerating Automotive Functional Safety Assessments Mountain View, California and Tempe, Arizona, Feb. 4, 2019/PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS) and FABU Technology Co., Ltd. today announced that FABU has selected a portfolio of silicon-proven Synopsys...

Read More »
Synopsys Introduces ARC EM Software Development Platform with an External Bus Interface
Controls & Controllers

Synopsys Introduces ARC EM Software Development Platform with an External Bus Interface

The DesignWare® ARC® EM Software Development Platform consists of hardware and software configuration information for speeding software development and debugging. The product comes with peripheral interfaces such as USB, SD card, Bluetooth, WiFi and 9D motion sensor digital microphone input. It provides online access to device drivers, examples and open-source software. The platform supports...

Read More »
Synopsys Introduces Fusion Compiler That is Designed for RTL-to-GDSII Implementation
Electronic Components & Devices

Synopsys Introduces Fusion Compiler That is Designed for RTL-to-GDSII Implementation

The Fusion Compiler™ combines high-capacity synthesis technology and an IC Compiler™ II route technology. The compiler is built-on single data model that supports common signoff analysis, optimization, concurrent clock data optimization, clock topology creation, and routing engines. This compiler is suitable for the design of FinFET-based automotive applications.

Read More »
Latest DesignWare STAR Memory System Comes with Enhanced Design Acceleration Scripts
Software

Latest DesignWare STAR Memory System Comes with Enhanced Design Acceleration Scripts

The DesignWare STAR Memory System is embedded with suite of test, repair, and diagnostic capabilities for optimizing MRAM test time. The system is offered with new algorithms that target failure mechanisms of embedded MRAM. It supports multiple background patterns and complex addressing modes and accelerates the ATE vector generation. The STAR Memory System is able to test, diagnose, and debug a...

Read More »
Latest Custom Compiler Custom Design Tool is Now Available with Visually-Assisted Automation
Software

Latest Custom Compiler Custom Design Tool is Now Available with Visually-Assisted Automation

Synopsys offers the Custom Compiler™ Custom Design Tool version 2018.09 with performance improvements and enhancements that reduce the time to design closure for custom IC design. The tool is now added with Extraction Fusion and DRC Fusion with IC validator. The compiler’s visually-assisted automation technology automates custom layout tasks and the template assistant provides the ability to...

Read More »
New FineSim SPICE Circuit Simulation Software Comes with Extraction Fusion and DRC Fusion Technologies
Software

New FineSim SPICE Circuit Simulation Software Comes with Extraction Fusion and DRC Fusion Technologies

The FineSim SPICE Circuit Simulation Software is embedded with RF analysis features, StarRC and IC validator. The software enables tighter design/layout collaboration and fewer late-stage design iterations. It comes with custom layout editor with advanced technologies for parasitic extraction, reliability analysis, and physical verification. The visually-assisted automation of the software is...

Read More »
Synopsys Releases New Platform Architect Ultra for Cloud and Edge Applications
Software

Synopsys Releases New Platform Architect Ultra for Cloud and Edge Applications

The Platform Architect™ Ultra Architecture Exploration, Analysis and Design Solution comes with AI reference system that enables integration, analysis and optimization of CNN workload models. This software maps CNN algorithms and workloads to explore processing and memory architecture options. It allows architects to analyze, select, optimize, and tune algorithms and architectures. The...

Read More »

All Topics