Synopsys, Inc.
690 East Middlefield Road
Mountain View, CA 94043
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Synopsys Enables First-Pass Silicon Success of High Performance NSITEXE Data Flow Processor-based SoC Test Chip for Autonomous Driving
NSITEXE Adopts Synopsys Design, Verification and IP Solutions to Accelerate the Development of New Processor Chip MOUNTAIN VIEW, Calif., Sept. 3, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that NSITEXE, Inc. achieved success with its first silicon for Data Flow Processor (DFP)-based SoC test chip by using Synopsys design, verification and IP solutions. The DFP has a unique...
Read More »Synopsys Enables First-Pass Silicon Success of High Performance NSITEXE Data Flow Processor-based SoC Test Chip for Autonomous Driving
NSITEXE Adopts Synopsys Design, Verification and IP Solutions to Accelerate the Development of New Processor Chip MOUNTAIN VIEW, Calif., Sept. 3, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that NSITEXE, Inc. achieved success with its first silicon for Data Flow Processor (DFP)-based SoC test chip by using Synopsys design, verification and IP solutions. The DFP has a unique...
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Samsung Accelerates New Product Ramp for 7nm Technology Node Using Synopsys' Yield Explorer
Comprehensive Yield Learning Platform from Synopsys Enables Close Collaboration with Samsung and Its Fabless Customers During Production Ramp-up of New Products MOUNTAIN VIEW, California, Aug 7, 2019 /PRNewswire/ -- Highlights: Collaboration between Samsung and Synopsys results in fast product ramp for 10/8/7nm products and establishes a foundation for yield learning for 5/4/3nm technology nodes...
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Samsung Accelerates New Product Ramp for 7nm Technology Node Using Synopsys' Yield Explorer
Comprehensive Yield Learning Platform from Synopsys Enables Close Collaboration with Samsung and Its Fabless Customers During Production Ramp-up of New Products MOUNTAIN VIEW, California, Aug 7, 2019 /PRNewswire/ -- Highlights: Collaboration between Samsung and Synopsys results in fast product ramp for 10/8/7nm products and establishes a foundation for yield learning for 5/4/3nm technology nodes...
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New IC Compiler II for Complex Next-generation Designs
Provides ten percent total power reduction, five percent smaller area, five percent better timing and 2X faster runtime. Delivers QoR and TTR for various markets including automotive, cloud computing, AI, networking and wireless applications. Arc-based unified CCD optimization, physically-aware logic re-synthesis and dynamic voltage drop-driven power shaping.
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New IC Compiler II for Complex Next-generation Designs
Provides ten percent total power reduction, five percent smaller area, five percent better timing and 2X faster runtime. Delivers QoR and TTR for various markets including automotive, cloud computing, AI, networking and wireless applications. Arc-based unified CCD optimization, physically-aware logic re-synthesis and dynamic voltage drop-driven power shaping.
Read More »
Enables Designers to Conceptualize Designs for Automotive Lighting
Supports accurate analyses of illuminance and irradiance on curved surfaces. Can analyze, measure, and visualize color effects directly in the part design view. Allow designers to perform comprehensive optical simulations and analyses of automotive lighting products.
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Enables Designers to Conceptualize Designs for Automotive Lighting
Supports accurate analyses of illuminance and irradiance on curved surfaces. Can analyze, measure, and visualize color effects directly in the part design view. Allow designers to perform comprehensive optical simulations and analyses of automotive lighting products.
Read More »
Synopsys Releases Verification Continuum Platform That Enables to Uncover Dead Code in Minutes
Offered with enhanced native integrations that enable performance gains between all verification engines. Integration with SpyGlass and VCS Unified Compile provides seamless read of DesignWare® IP and encrypted IP designs. Delivers a unified compile of design and testbench and low latency interface that support seamless mix of signal-level and transaction-level communication.
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Synopsys Releases Verification Continuum Platform That Enables to Uncover Dead Code in Minutes
Offered with enhanced native integrations that enable performance gains between all verification engines. Integration with SpyGlass and VCS Unified Compile provides seamless read of DesignWare® IP and encrypted IP designs. Delivers a unified compile of design and testbench and low latency interface that support seamless mix of signal-level and transaction-level communication.
Read More »