Synopsys, Inc.
Mountain View, CA 94043
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Synopsys and TSMC Collaborate for Certification on 5nm Process Technologies to Address Next-Generation HPC, Mobile Design Requirements
Enhancements in Design and Verification Tools Target Gains in Performance and Ultra-low Power MOUNTAIN VIEW, California, Nov. 25, 2019 /PRNewswire/ -- Highlights: Tools certified for the latest version of TSMC's N5/N5P DRM and SPICE model Synopsys power optimization enabled to support ultra-low power requirement of mobile devices Implementation vs. signoff correlation, certified for timing and...
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New VC LP Solution for Low-power Signoff and Static Verification
Includes SAM based methodology, which enabled to achieve up to 5X performance gains and up to 6X less memory footprint with the same QoR. Contains machine learning-enabled analysis technology for improved QoR and high debugability. Reduces the overall turnaround time for verification signoff to ensure that subtle bugs do not escape into silicon.
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Synopsys DesignWare ARC Data Fusion IP Subsystem Incorporated by Himax in Their Artificial Intelligence WiseEye ASIC
Always-On Sensing ASIC Enables Machine Learning for Ultra-Low Power Applications MOUNTAIN VIEW, Calif., Nov. 12, 2019 /PRNewswire/ -- Highlights: Himax WiseEye ASIC platform is optimized for application developers deploying machine learning on battery-powered AIoT devices Synopsys DesignWare ARC Data Fusion IP Subsystem with audio software library, tightly coupled pulse density modulation...
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New TestMAX XLBIST Solution Provide Dynamic In-system Testing for Critical Failures
Delivers high fault coverage and shorter test time by overcoming silicon issues that impede self-test solutions. Enables design teams to minimize implementation turnaround time. Avoids issues such as iterative design modifications and significant silicon area increases and prolonged schedules that are common to previous in-system test technologies.
Read More »Device Controller IP comply with DSI v1.2 and CSI-2 v1.2 specs.
Respectively supporting up to- 8 and- 4 lanes of operation, DesignWare-® MIPI-® CSI-2SM Device Controller IP and DesignWare MIPI DSISM Device Controller IP let designers implement required camera and display functionality in mobile, automotive, and IoT applications. Both device controllers, interoperable with DesignWare MIPI D-PHY v1.2 operating at 2.5 Gbps/lane, offer integrated debug and...
Read More »Synopsys TetraMAX II ATPG Certified for ISO 26262 Automotive Functional Safety
Independent Functional Safety Evaluation Provides Highest Level of Safety-Related Tool Confidence MOUNTAIN VIEW, Calif. - Highlights: Tool certification accelerates ISO 26262 functional safety qualification for automotive ICs up to the most stringent safety requirements for ASIL D Enables automotive IC design teams to accelerate their manufacturing test development process with 10X faster run...
Read More »Synopsys TetraMAX II Speeds Test Generation for STMicroelectronics SoC Designs
New ATPG Engines Substantially Reduce Test Pattern Count for Lower Test Cost MOUNTAIN VIEW, Calif. - Highlights: Evaluation of TetraMAX II demonstrated an order of magnitude speedup in runtime Achieves significant test-pattern-count reduction without impacting test coverage Synopsys, Inc. (Nasdaq: SNPS), today announced that STMicroelectronics is seeing significantly faster test pattern...
Read More »Test Pattern Generator cuts ATPG runtime from days to hours.
Built on test generation, fault simulation, and diagnosis engines that are extremely fast, TetraMAX-® II ensures patterns are ready when early silicon samples are first available for testing. Pattern reduction enables designers to shorten time of testing, while memory efficiency enables utilization of all server cores regardless of design size. Reuse of design modeling and rule checking...
Read More »SMIC and Synopsys Deliver 28-nm HKMG Low-Power Reference Flow
Collaboration Delivers Best-In-Class Power, Performance and Area with IC Compiler II MOUNTAIN VIEW, Calif. and SHANGHAI - Highlights: - - - --- Technology advancements in the latest release of IC Compiler II deliver - - - - - - - exceptional quality-of-results across all key metrics: Better - - - - - - - performance, smaller area and lower power - - - --- Speeds design...
Read More »Medium Density NVM brings flash to 5 V CMOS and BCD processes.
Available in TSMC 180 nm 5 V CMOS and BCD process technologies, DesignWare-® Medium Density Non-Volatile Memory (NVM) IP provides up to 64 kB on-chip memory and eliminates need for external EEPROM or flash memory when integrating MCUs in analog IC designs. Additional system reliability is afforded via error checking and correction functionality, -40 to +125-
Read More »Synopsys and Samsung Foundry Collaboration Delivers High-Performance Physical Signoff on Samsung SAFE Cloud Design Platform
IC Validator Delivers 30 Percent Compute Savings with Dynamic Elastic CPU on Cloud MOUNTAIN VIEW, Calif., April 6, 2021 /PRNewswire/ -- Highlights: Collaboration enables on-demand IC Validator physical signoff on Samsung SAFE Cloud Design Platform Synopsys IC Validator cloud optimized technology enables massive scaling and efficient resource usage for fast design closure Rescale and Microsoft...
Read More »Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification
Highlights: Industry's first SoC power-aware emulation system for multi-billion gate designs enables hardware-software power verification with software workloads The industry's fastest emulation system – with high performance power verification engines – enables multiple iterations per day ZeBu Empower feeds power critical blocks and time windows into PrimePower, the industry's golden...
Read More »Synopsys Receives Customer's Choice Award for Paper Presented at TSMC 2020 Open Innovation Platform Ecosystem Forum
Award-Winning Paper Features 5nm Node Enablement and Maximizing QoR With Synopsys Fusion Compiler RTL-to-GDSII Implementation System Solution Mountain View, Calif., Feb. 9, 2021 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced it received the Customers' Choice Award for a technical paper presented at the TSMC 2020 North America Open Innovation Platform® (OIP) Ecosystem Forum....
Read More »Synopsys Selected for Rapid Assured Microelectronics Prototypes Program
Collaboration with Microsoft To Create a Secure Design Environment while Enabling Assurance throughout the Silicon Lifecycle MOUNTAIN VIEW, Calif., Feb. 4, 2021 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that it is collaborating with Microsoft in the Rapid Assured Microelectronics Prototypes (RAMP) program to support the development of integrated circuit hardware and...
Read More »Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5-Nanometer Process in AI and High-Performance Computing SoCs
Collaboration Builds on Successful Adoption of Broad DesignWare IP Portfolio in Socionext's High-Performance AI Engine and Accelerator Solution MOUNTAIN VIEW, Calif. and YOKOHAMA, Japan, Jan. 12, 2021 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) and Socionext, Inc. today announced their collaboration to expand Socionext's use of Synopsys' broad DesignWare® IP to include...
Read More »Synopsys and Samsung Foundry Collaborate to Deliver Fastest Design Closure and Signoff for Process Nodes Down to 3nm
Highlights: Collaboration includes multiple signoff domains and spans library characterization to full-chip signoff for accelerated design closure Signoff solution innovations address unique challenges from 5nm to 3nm to ensure signoff accuracy with 20X faster runtime and half the memory consumption Customer productivity enhanced by 5X reduction in ECO iterations and better hardware efficiency...
Read More »Synopsys Acquires In-chip Monitoring Solutions Leader Moortec
Acquisition Expands Silicon Lifecycle Management Platform to Include Critical PVT Sensor Data for Greater Chip and System Optimizations MOUNTAIN VIEW, Calif., Nov. 11, 2020 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS) today announced that it has acquired Moortec, a leading provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. The Moortec...
Read More »Synopsys Wins Multiple 2020 World Electronics Achievement Awards
DSO.ai Design Space Optimization System Named Innovative Product of the Year and VC SpyGlass RTL Static Signoff Solution Honored as Most Promising Chip Life Technology MOUNTAIN VIEW, Calif., Nov. 5, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced it received two 2020 World Electronics Achievement Awards (WEAA): Innovative Product of the Year for DSO.ai™ (Design Space...
Read More »Synopsys and Samsung Foundry Collaboration Delivers Optimized Reference Methodology for High-performance Compute Designs
Synopsys Fusion Design Platform Enables Full-Flow Quality-of-Results and Fastest Design Convergence on Samsung Advanced Process Technology Highlights: Synopsys and Samsung have collaborated on the enablement of Fusion Design Platform to unleash the benefits of Samsung's most advanced process nodes Certified flow provides designers a complete suite of industry-leading digital implementation and...
Read More »TSMC Recognizes Synopsys Collaboration with Four OIP Partner of The Year Awards for IP and EDA Solutions
Highlights: Synopsys selected as TSMC OIP Partner of the Year for interface IP and tool enablement for the 10th consecutive year Collaborations on interface IP, joint development of 3nm design infrastructure, 3DIC design productivity solution and a highly scalable timing sign-off in the cloud are recognized Mountain View, Calif., Oct. 20, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS)...
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