Synopsys, Inc.
Mountain View, CA 94043
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New DesignWare IP Software Provides Adaptive DSP Algorithms
Delivers 64 GT/s data rate with low latency for high-performance computing, AI and storage SoCs. Offers high-performance PHY in 5-nm process with unique analog and DSP techniques. Protocol, methodology and productivity features enable rapid verification of PCI Express 6.0 designs.
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Latest Illumination Design Software Comes with Improved Optomechanical Interoperability
Enhanced LiDAR design features, increased ray tracing speed, and faster optomechanical modeling with Solidworks. Features distributed simulation module that increases the speed of computation-intensive ray tracing. Users can design laser sources with gaussian and super gaussian light distributions using spatial and angular apodization.
Read More »New CXL 2.0 VIP Software Designed for Data-Intensive SoCs
Features built-in coverage, verification planning, and memory-aware debug and performance analysis. Uses SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments. Supporrts all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.
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Latest Virtualizer Development Kit is Ideal for Automotive Companies
Supports Infineon's AURIX TC4xx 32-bit microcontroller with parallel processing unit. Enables early investigation and testing of algorithm implementations for AI and deep learning solutions. Provides external communication, co-simulation and debug/test interfaces for software debugging, virtual hardware-in-the-loop testing, and calibration and fault testing.
Read More »Synopsys Demonstrates Industry's First PCI Express 5.0 IP Interoperability with Intel's Future Xeon Scalable Processor
Successful Interoperability Enables Low-Risk Integration and Broad Adoption of the PCIe 5.0 Interface in High-Performance Computing SoCs MOUNTAIN VIEW, Calif., Oct. 13, 2020 /PRNewswire/ -- Highlights: Interoperability establishes end-to-end 32GT/s PCIe 5.0 link between DesignWare IP for PCI Express 5.0 Complete Solution and future Intel Xeon Scalable processors The DesignWare IP for PCI...
Read More »Latest DesignWare CXL IP Software Operates at 32GT/s with 512-bit Data Width
Supports AMBA CXS protocol to enable seamless integration with scalable Arm Neoverse Coherent Mesh Network. Extended capabilities across Arm-based SoCs requiring cache coherency and fast chip-to-chip interconnects. Delivers extremely low-latency and high-bandwidth.
Read More »New EM22FS Functional Safety Processor IP is ISO 26262 ASIL D Compliant
Offers integrated safety-critical hardware features such as dual-core lockstep, error-correcting code, and safety monitors, facilitate chip-level safety certification. Includes comprehensive safety documents such as failure modes, effects and diagnostic analysis (FMEDA), Safety Manual, Safety Case Report, ISO 26262 Functional Safety Assessment Report, and other safety-related documents. Developed...
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Synopsys ASIP Designer Tool has Ability to Export Processor's Simulation Model with SystemC Interfaces
ASIP Designer helps NSITEXE to optimize the processors multicore architecture and automatically generate software development kits. Allowed NSITEXE to specify the desired processor architecture in a high-level language at the abstraction level of a programmer's manual. Automatically configures the SDK containing a cycle-accurate instruction-set simulator, assembler, linker, debugger and C/C++...
Read More »Synopsys and Nestwave Collaborate to Develop a Low-power Geolocation IP Solution for IoT Modems
Combination of Synopsys' ARC IoT Communications IP Subsystem with Nestwave's Geolocation IP Eliminates the Need for a Dedicated Positioning Chipset Highlights: Nestwave's low-power geolocation solution incorporates Synopsys DesignWare ARC IoT Communications IP Subsystem with integrated ARC EM9D Processor IP ARC EM9D processor and custom instruction extensions provide performance boosts for...
Read More »New Integrated Solution Leverages Virtual Prototyping Technologies Including Virtualizer, Silver, TestWeaver and SaberRD
Support the needs of EV design which includes EV model libraries for power electronic, microcontrollers and AUTOSAR components. Enables more productive development and rapid scaling of test activities by removing the dependency on a physical hardware set up. Includes debug, analysis and test functionality to support functional safety, HW/SW debug, variation analysis, coverage analysis and...
Read More »Synopsys and Samsung Foundry Collaboration Delivers High-Performance Physical Signoff on Samsung SAFE Cloud Design Platform
IC Validator Delivers 30 Percent Compute Savings with Dynamic Elastic CPU on Cloud MOUNTAIN VIEW, Calif., April 6, 2021 /PRNewswire/ -- Highlights: Collaboration enables on-demand IC Validator physical signoff on Samsung SAFE Cloud Design Platform Synopsys IC Validator cloud optimized technology enables massive scaling and efficient resource usage for fast design closure Rescale and Microsoft...
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New DesignWare IP Software Provides Adaptive DSP Algorithms
Delivers 64 GT/s data rate with low latency for high-performance computing, AI and storage SoCs. Offers high-performance PHY in 5-nm process with unique analog and DSP techniques. Protocol, methodology and productivity features enable rapid verification of PCI Express 6.0 designs.
Read More »Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification
Highlights: Industry's first SoC power-aware emulation system for multi-billion gate designs enables hardware-software power verification with software workloads The industry's fastest emulation system – with high performance power verification engines – enables multiple iterations per day ZeBu Empower feeds power critical blocks and time windows into PrimePower, the industry's golden...
Read More »Synopsys Receives Customer's Choice Award for Paper Presented at TSMC 2020 Open Innovation Platform Ecosystem Forum
Award-Winning Paper Features 5nm Node Enablement and Maximizing QoR With Synopsys Fusion Compiler RTL-to-GDSII Implementation System Solution Mountain View, Calif., Feb. 9, 2021 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced it received the Customers' Choice Award for a technical paper presented at the TSMC 2020 North America Open Innovation Platform® (OIP) Ecosystem Forum....
Read More »Synopsys Selected for Rapid Assured Microelectronics Prototypes Program
Collaboration with Microsoft To Create a Secure Design Environment while Enabling Assurance throughout the Silicon Lifecycle MOUNTAIN VIEW, Calif., Feb. 4, 2021 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that it is collaborating with Microsoft in the Rapid Assured Microelectronics Prototypes (RAMP) program to support the development of integrated circuit hardware and...
Read More »Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5-Nanometer Process in AI and High-Performance Computing SoCs
Collaboration Builds on Successful Adoption of Broad DesignWare IP Portfolio in Socionext's High-Performance AI Engine and Accelerator Solution MOUNTAIN VIEW, Calif. and YOKOHAMA, Japan, Jan. 12, 2021 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) and Socionext, Inc. today announced their collaboration to expand Socionext's use of Synopsys' broad DesignWare® IP to include...
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Latest Illumination Design Software Comes with Improved Optomechanical Interoperability
Enhanced LiDAR design features, increased ray tracing speed, and faster optomechanical modeling with Solidworks. Features distributed simulation module that increases the speed of computation-intensive ray tracing. Users can design laser sources with gaussian and super gaussian light distributions using spatial and angular apodization.
Read More »Synopsys and Samsung Foundry Collaborate to Deliver Fastest Design Closure and Signoff for Process Nodes Down to 3nm
Highlights: Collaboration includes multiple signoff domains and spans library characterization to full-chip signoff for accelerated design closure Signoff solution innovations address unique challenges from 5nm to 3nm to ensure signoff accuracy with 20X faster runtime and half the memory consumption Customer productivity enhanced by 5X reduction in ECO iterations and better hardware efficiency...
Read More »Synopsys Acquires In-chip Monitoring Solutions Leader Moortec
Acquisition Expands Silicon Lifecycle Management Platform to Include Critical PVT Sensor Data for Greater Chip and System Optimizations MOUNTAIN VIEW, Calif., Nov. 11, 2020 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS) today announced that it has acquired Moortec, a leading provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. The Moortec...
Read More »New CXL 2.0 VIP Software Designed for Data-Intensive SoCs
Features built-in coverage, verification planning, and memory-aware debug and performance analysis. Uses SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments. Supporrts all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.
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