New ARC VPX DSP Processor IP Can Deliver 512 FLOPs and 32 Math Operations Per Cycle
Signal Processors

New ARC VPX DSP Processor IP Can Deliver 512 FLOPs and 32 Math Operations Per Cycle

Supports single-, dual-, and quad-core configurations and contains scalar execution unit and multiple vector computation units that support 8-bit, 16-bit, and 32-bit SIMD computations. Incorporates ultra-wide vector architecture to accelerate highly parallel automotive, sensor fusion, and communications applications. Offers ARC MetaWare development toolkit with C/C++ compiler and associated...

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New ARC VPX DSP Processor IP Can Deliver 512 FLOPs and 32 Math Operations Per Cycle
Signal Processors

New ARC VPX DSP Processor IP Can Deliver 512 FLOPs and 32 Math Operations Per Cycle

Supports single-, dual-, and quad-core configurations and contains scalar execution unit and multiple vector computation units that support 8-bit, 16-bit, and 32-bit SIMD computations. Incorporates ultra-wide vector architecture to accelerate highly parallel automotive, sensor fusion, and communications applications. Offers ARC MetaWare development toolkit with C/C++ compiler and associated...

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Processors

Synopsys, Customers, and Partners Present The Latest Trends and Technologies in Embedded Processor Solutions at the Synopsys ARC Processor Summit

Attendees Will Learn About Solutions to Address Design Challenges in Artificial Intelligence, Machine Learning, Embedded Vision, Automotive Safety, and IoT Applications Mountain View, Calif., Sept. 9, 2019 /PRNewswire/ -- When: Thursday, September 19 from 9:30 a.m. to 5:30 p.m. Where: Santa Clara Marriott, 2700 Mission College Blvd, Santa Clara, CA 95054 Register: www.synopsys.com/ARCsummit...

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