Design System provides hierarchical access to parameters.

SPW 4.8 Signal Processing Worksystem block diagram design solution allows hardware, software, and RF engineers to collaborate on projects. Links with other tools include integrations with Xilinx Coregen solution, with analog design flow that supports Cadence(R) AMS Designer, and with SystemC 2.0. SPW 4.8 users can enter and simulate designs consisting of various types of models including C, C++,...

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Digital Signal Processor operates at 250 MHz.

ADSP-TS101S TigerSHARC DSP offers 250 MHz clock rate, 1500 MFLOPS performance and native support for 8, 16, 32, and 40-bit data types. It has 1.5 W power dissipation, 6 Mbit of on-chip memory, 14 channel zero-overhead DMA engine, integrated SDRAM controller, parallel host interface, cluster multiprocessing support, and link port multiprocessing support. Applications include data acquisition,...

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Octal DSP Boards transfer data at 600 MB/sec.

Octal TMS320C6203 DSPs are 6U VME COTS boards that feature both PMC (PCI Mezzanine Card) and VIM (Velocity Interface Mezzanine) interface. VIM mezzanine delivers 1200 Mbytes/sec of I/O data directly to processors, and eight C6203 DSPs provide 19,200 MIPS peak processing power. C6203's VLIW engine executes up to 8 instructions in one 300 MHz clock cycle. DMA controllers transfer data to SDRAM and...

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