Press Release Summary:
Expanding on interleaved multi-channel technology (IMT), SonicsGNÂ® 3.0 includes layout optimization features for design flows based on physical synthesis as well as placeÂ and route tools. SoCÂ designers can eliminate multi-channel DRAM access bottlenecks with IMT and reduce layout tool iterations with flexible user control of hierarchical RTL partitioning and re-timing stage insertion. Also included, flexible reordering buffer architecture enhances concurrency.
Original Press Release:
Sonics Improves NoC Concurrency Management for SoC Designs with Multi-Channel Memory Sub-Systems, Addresses Place & Route Tool Restrictions
SonicsGN 3.0 Expands Patented IMT to Exploit Transaction Parallelism and Increases User Control of Hierarchical RTL Partitioning to Guide Physical Design
MILPITAS, Calif. -- Sonics, Inc., the world's foremost supplier of on-chip network (NoC) technologies and services, today released SonicsGN(®) 3.0, the latest version of the company's flagship NoC. SonicsGN 3.0 expands on the interleaved multi-channel technology (IMT) that has been patented and proven in SonicsSX(®) and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools. SoC architects using SonicsGN 3.0 can eliminate multi-channel DRAM access bottlenecks with IMT and reduce layout tool iterations with flexible user control of hierarchical RTL partitioning and re-timing stage insertion.
"We originally patented IMT in 2008 and it has been routinely implemented by many of our SonicsSX(®) customers. At that time, SoC designers were early in the move to multi-channel memory architectures," said Drew Wingard, CTO of Sonics. "Use of multi-channel DRAMs and memory sub-systems is now pervasive in SoC designs, for example, in mobile applications where maximizing memory throughput takes precedence over increasing memory capacity. To address this trend, we've expanded IMT in SonicsGN 3.0 to give SoC architects much more effective management of transaction concurrency and memory sub-system performance in their designs. At the same time, we've enhanced SonicsGN's handling of hierarchical partitioning and re-timing to provide better layout guidance when designers generate their RTL netlist for physical synthesis and detailed place & route."
Concurrency Management for More Efficient DRAM Access and Transaction Ordering
In SoC designs with multi-channel DRAM subsystems, the processor speed and the total number of processors has grown to the point that the memory bandwidth bottleneck is the biggest problem. The purpose of using multi-channel memory is to exploit parallel access to memory, while avoiding bandwidth loss due to wide DRAM data buses. By breaking data into smaller word sizes and interleaving the transactions across multiple channels, IMT enables designers to improve concurrency and overall throughput by up to 20 percent using the same external DRAMs.
Another related concurrency management problem is ordering of requests that may be simultaneously outstanding to multiple targets, including multi-channel memories. SonicsGN's flexible reordering buffer architecture enables single initiator agents to have transactions outstanding to an arbitrary collection of targets, while respecting the protocol-defined ordering. SoC designers using the reordering buffer can further enhance concurrency by creating separate transaction tags where none existed or by restricting the reordering behavior.
Layout-Optimized RTL Netlist Generation
SonicsGN provides SoC designers a single, unified network that simplifies design capture and makes consistent the description of how addresses and connectivity work across an entire fabric that may span multiple clock, voltage and/or power domains. SonicsGN automatically generates the RTL hierarchies that respect the clock, power, and voltage domain boundaries for the physical tools. SonicsGN 3.0 includes new, user-controlled hierarchical partitioning and re-timing stage insertion capabilities that give designers control of which domains are associated with each re-timing stage for internal network links. Using these features, designers can better structure their SoC designs and optimize RTL netlist generation for physical layout, which results in fewer iterations in the back-end design flow.
SonicsGN 3.0 is available to early access customers now with general availability in July. For more detailed information on IMT, download the white paper. For more information on SonicsGN 3.0, contact your Sonics sales representative.
About Sonics, Inc.
Sonics, Inc. (Milpitas, Calif.) is the trusted global leader in on-chip network (NoC) technologies used by the industry's top semiconductor and electronics product companies. Sonics was the first company to develop and commercialize NoCs, accelerating volume production of complex systems-on-chip (SoC) that contain multiple processor cores. Our comprehensive NoC portfolio delivers the communication performance required by today's most advanced consumer digital, communications and information technology devices. Sonics' NoCs are integral to the success of SoC design platforms that innovators such as Broadcom®, Intel®, Marvell®, MediaTek, and Microchip® rely on to meet their most demanding SoC integration and time-to-market requirements. We are a catalyst for design methodology change and actively drive industry conversation on the Agile IC LinkedIn group. Sonics' holds approximately 150 patent properties supporting customer products that have shipped more than four billion SoCs. For more information, visit sonicsinc.com, and follow us on Twitter at twitter.com/sonicsinc.
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