Memory Test System suits wafer/package level NAND testing.
Press Release Summary:
With parallel test capacity of up to 512 devices, Model T5761 features ECC, real-time counter to calculate number of fail bits, and flash memory block management that allows skipping unneeded blocks without testing. Model T5761ES offers up to 16 devices test capacity and simplifies low-volume device evaluation and facilitates development of test programs for high-volume production. Models T5761/T5761ES have maximum speed of 66 MHZ and utilize tester-per-site architecture.
Original Press Release:
Advantest Launches New T5761/T5761ES Memory Test System
512-Device Parallel Test Capacity Offers High Throughput for Wafer and Package Level NAND Testing
TOKYO, Nov. 2 -- Advantest Corporation , (NYSE:ATE), today announced that its new memory test system, the T5761/T5761ES, for NAND flash memory wafer test and package test. The system, which will be available from December 1, 2006, and the company will exhibit the new NAND test solution during SEMICON Japan, December 6-8, at the Makuhari Messe in Chiba, Japan.
Growth in consumer electronics such as cellular phones, digital cameras, and MP3 players continues to accelerate demand for NAND flash memory, and the market is forecast to expand further as NAND applications evolve to include storage media such as hard disks for personal computers. However, while device bit density grows rapidly, and devices become faster and more reliable, cost-per-bit is plummeting. Semiconductor equipment manufacturers are being called upon to provide efficient, low-cost test solutions that can enhance throughput and yield.
Ideal Solution for Cost-Efficient NAND Development and Production
Advantest's new T5761/T5761ES test system utilizes tester-per-site architecture, the optimal choice for flash memory test, to maximize efficiency at every stage of NAND test from wafer test to package test. With a 512-device parallel test capacity -- twice that of the company's previous model -- the new system delivers dramatically higher throughput. It also boasts a new error correction function (ECC) specially developed for NAND devices, thus improving yield. In addition, a real-time counter calculates the number of fail bits while the tester is in operation, and its upgraded NAND flash memory block management ability allows it to skip unneeded blocks without testing them, contributing to reduced test times. Though equipped with added functionality, the T5761/T5761ES is offered at a price equivalent to or less than that of its predecessor.
With its low cost, added functionality and industry-leading utilization, the T5761/T5761ES provides flash memory producers with an optimal manufacturing solution.
The T5761ES (Engineering Solution) shares all the functionality and performance of the T5761, but it has been specially designed to simplify low-volume device evaluation and facilitate the development of test programs for high-volume production. Both models offer unique advantages for NAND flash memory testing needs from engineering through production.
Key Specifications
T5761
Parallel Test Capacity: max. 512 devices
Maximum Test Speed: 66MHz
Test Head: 1 station
T5761ES
Parallel Test Capacity: max. 16 devices
Maximum Test Speed: 66MHz
Test Head: 1 station
Source: Advantest Corporation
CONTACT:
Amy Gold
Advantest America, Inc.
+1-212-850-6670
a.gold@advantest.com
Web site: http://www.advantest.com/
