Ethernet Controller IC has TCP/IP core and MAC/PHY interface.

Press Release Summary:




Designed for high-speed embedded systems, Model W5300 10/100 Ethernet controller IC offers stable speeds up to 50 Mbps and supports 8 independent, simultaneous sockets with 16- or 8-bit data bus. It supports hybrid TCP/IP stacks, as well as Ethernet protocols with internal hardware including TCP, UDP, ICMP, IPv4, ARP, IGMP, and PPPoE. Using internal 150 MHz core, IC dynamically allocates its internal 128 Kb Tx/Rx memory according to socket throughput.



Original Press Release:



W5300 - New Embedded-Internet IC with Fully-Hardwired TCP/IP Core and PHY Interface Designed for High-Speed Embedded Systems.



Pittsford, NY: W5300 is a new, full-featured 10/100 Ethernet controller IC from WIZnet, three times as fast and with double the channels of its predecessor W5100.

W5300, with built-in MAC and PHY, offers stable speeds up to 50 Mbps - enough to watch movies in real-time rather than buffered. W5300 supports eight independent, simultaneous sockets, with a 16- or 8- bit data bus. W5300 is as simple to control as a memory IC and is capable of even supporting, for instance, simultaneous broadband access, VoIP, and digital broadcasting.

Supporting most Ethernet Protocols (TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE) with internal hardware, W5300 also supports hybrid (software and hardware) TCP/IP stacks. Using an internal 150MHz core, W5300 dynamically allocates its internal 128Kbyte Tx/Rx memory according to socket throughput.

W5300 includes a fully hardwired TCP/IP core as well as a PHY interface layer and is designed for embedded applications where ease of integration, stability, high performance, size, and low system cost are important considerations. W5300 is a memory-mapped hardware TCP/IP solution that allows even low-end microcontrollers ready-made Internet capabilities at full speed with no need for additional PHY layer ICs.

W5300 allows engineers to off-load the burden of the TCP/IP stack into a second peripheral chip (complete with Ethernet MAC and PHY) with few peripheral components. This reduces product debug issues and speeds time-to-market with the design of the TCP/IP stack avoided, and the additional benefit of a more stable product. Simple 8-bit micros immediately have much more power since they no longer have the burden of TCP/IP protocols. TCP- offload improves overall system performance, reduces cost, power and size, increases robustness. Engineers no longer need to have detailed knowledge of TCP/IP since this is all accomplished within the W5300.

W5300's fully hardwired TCP/IP algorithm guarantees line speed with on-the-fly processing architecture that is independent of the main processor. It also eliminates a main processor's overhead by offloading network tasks, thus enhancing overall system performance - vital in multimedia streaming applications. Direct and indirect bus addressing is provided, as well as an SPI interface, for simple interfacing.

Designed by Korea's Ethernet specialists WIZnet, this hardwired TCP/IP chip technology has been adopted worldwide both in OS-less devices (e.g. DVR, Remote Control) and OS-based (e.g. set- top Boxes, DTV, media controllers). It provides higher performance and stability than any software Internet connectivity solution. Advantages of incorporating the TCP/IP stack in an IC include: system robustness, faster time-to-market, up to 25Mbps for even low-end microcontrollers or even non-OS systems. W5300 is aimed at applications that include media- streaming, home networking, serial-to-Ethernet, parallel-to-Ethernet, USB-to-Ethernet, security systems, factory automation, medical equipment, etc.

W5300 will be available in May, 2008 from WIZnet's USA distributor Saelig Company at $5.99 (1K qty). 1-888-7SAELIG info@saelig.com www.saelig.com

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