Press Release Summary:
Designed for APS family of 32-bit processor IP cores, APS-DSP optimizes data handling to support multimedia and other demanding analog or mixed-signal applications. Fixed-point, 16-bit unit adds 3 arithmetic logic units operating in parallel, as well as 2 memory interfaces, and uses Harvard bus architecture for memory design. Bit-reverse arithmetic feature facilitates DSP calculations, while Zero Overhead Loop hardware enables efficient data processing.
Original Press Release:
CAST Releases DSP Coprocessor for Cortus APS 32-Bit Processor Cores
APS-DSP Coprocessor helps overcome the programming and hardware challenges of Digital Signal Processing applications for the 8051 upgrade market
SAN JOSE, Calif., May 22 /-- InStat Microprocessor Forum -- Semiconductor intellectual property (IP) provider CAST, Inc. today announced the availability of a Digital Signal Processing (DSP) coprocessor for the APS family of 32-bit processor IP cores.
Introduced a year ago, the APS family brings 32-bit processing power to designers more familiar with 8051s and other 8-bit microcontrollers. The new APS-DSP continues this approach, offering simple programming and adding fast math operations and optimized data handling to effectively support multimedia and other demanding analog or mixed-signal applications.
"Customers have found that APS delivers a real sweet-spot combination of fast processing, small area, and low power that's perfect for many applications," said Hal Barbour, president of CAST. "This easy DSP coprocessor means designers can now succeed in an exploding market where products need to have voice recognition, streaming video, or other slick features just to get noticed."
The APS-DSP and the APS family of processors are developed by CAST partner Cortus, S.A. in France. The coprocessor is available now as an integrated add- on to the APS2 and APS3 processor cores, and is ready for implementation in ASICs, structured ASICs, or FPGAs.
About the APS-DSP
The APS-DSP is a fixed point, general purpose, 16-bit extension to the APS family of processors. It expands the APS instruction set with special DSP functions, and adds additional processing and memory interface hardware to significantly improve performance for complex arithmetic calculations.
The patented coprocessor interface built into APS processors enables tight integration and parallel operation of the DSP and main CPU functions. This means instructions complete in a single cycle, with the DSP coprocessor and the main processor executing instructions at the same speed, and with out-of- order instruction completion.
The coprocessor adds three arithmetic logic units (ALUs) operating in parallel, improving performance by enabling one arithmetic operation and two address calculations on every clock cycle. It adds two memory interfaces for greater memory bandwidth, and uses a Harvard bus architecture for simple memory design. A bit-reverse arithmetic feature facilitates certain DSP calculations, and special Zero Overhead Loop (ZOL) hardware enables smarter, more efficient data processing.
Instructions for the APS-DSP are written in efficient assembler language using a simple, straightforward, set of constructs. Provided macros make it easy to work with the DSP routines from the C and C++ programming environments of the APS processors. An included library offers pre-coded solutions for typical DSP challenges such as Fast Fourier Transforms (FFTs) and common architectures for both Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) digital filters. Designers can use these specific solutions without having the detailed DSP expertise necessary to implement the algorithms from scratch.
The 16-bit APS-DSP works with both members of the APS family, the 32-bit APS2 for high performance, and the 16/32-bit APS3 for dense code. Designed primarily as 8051 upgrades for deeply embedded systems, APS cores offer significantly more capability and speed than 8-bit processors while conserving silicon area, power, and cost compared to popular 32-bit processors. Multiple customers have selected APS over the past year, and the first customer designs are nearing production.
About Cortus S.A.
Cortus S.A. is a privately-held company that designs and licenses innovative, highly efficient 32-bit processor cores and IP around those processor cores. Designed to replace 8-bit controllers in deeply embedded systems, Cortus processors are uniquely small and power-efficient yet have advanced capabilities such as out-of-order instruction completion. The company is based in Montpellier, France. Learn more by visiting www.cortus.com.
About CAST, Inc.
CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operated since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia.
CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners.
CONTACT: Hal Barbour of CAST, Inc., +1-201-391-8300 ext. 111, firstname.lastname@example.org; or Michael Chapman of Cortus S.A., +33-4-67-13-01-90, email@example.com
Web site: www.cortus.com/