DRAM Load Simulator tests DRAMs encapsulated in BGAs.
Press Release Summary:
Measuring 8.0 x 13 x 1 mm, DLS1-DRAM Load Simulator for DDR1 has JEDEC standard footprint for x4, x8, or x16 organized devices on bottom and access points on top. Model DLS2-DRAM Load Simulator for DDR2 SDRAMs features JEDEC standard footprint for x4 or x8 organized devices and has dimensions of 11.6 x 14 x 1 mm. Both feature solder balls on surface to probe key DRAM I/O signals, and enable signals to be tested at point of origin or termination.
Original Press Release:
DRAM Load Simulator
Developed by Netlist, the DRAM load simulator (DLS) is a cost-effective way to test the loading conditions of DRAMs encapsulated in ball grid arrays (BGAs). Solder balls on the surface of the DLS provide a convenient mechanism to probe key DRAM I/O signals, which are inaccessible when the BGA is soldered to the substrate. Performance of high-speed DDR SDRAMs can be assessed without the expense of utilizing fully functional components. The DLS enables signals to be tested at the point of origin or termination, which is critical in high-speed designs.
DLS1-DRAM Load Simulator for DDR1
The Netlist DRAM Load Simulator for DDR1 SDRAMs (DLS1) is a substrate with a JEDEC standard footprint for x4, x8 or x16 organized devices on the bottom and access points on the top. Each signal pin is wired to an internal capacitor whose value matches the nominal loading that would be presented by an equivalent DRAM pin. This allows the DLS1 to be mounted in a memory system in place of a DDR1 SDRAM in order to test signal integrity of the memory design without disrupting signal quality.
DLS1-DRAM Load Simulator for DDR1 SDRAMs
Features:
o JEDEC standard footprint
- x4, x8, x16 devices
- MO-233A Var. AA
o Size: 8.0 x 13 x 1 mm
o Probe points for all DDR1 SDRAM signals
o 1.8 volts
o VSS flood for signal ground
o PC3200 (DDR 400)
o Load matching capacitors
- Cin = 2.0 pF
- Cio = 4.0 pF
DLS2-DRAM Load Simulator for DDR2
The Netlist DRAM Load Simulator for DDR2 SDRAMs (DLS2) is a substrate with a JEDEC standard footprint for x4 or x8 organized devices on the bottom and access points on the top. Each signal pin is wired to an internal capacitor whose value matches the nominal loading that would be presented by an equivalent DRAM pin. This allows the DLS2 to be mounted in a memory system in place of a DDR2 SDRAM in order to test signal integrity of the memory design without disrupting signal quality.
DLS2-DRAM Load Simulator for DDR2 SDRAMs
Features:
o JEDEC standard footprint
- x4, x8 devices
- MO-207 Var. DJ-z
o Size: 11.6 x 14 x 1 mm
o Probe points for all DDR2 SDRAM signals
o VSS flood for signal ground
o PC3200 (DDR 400)
o Load matching capacitors
- Cin = 1.5 pF
- Cio = 3.25 pF
