Design IP supports TSMC 16FFC and 28HPC+ process technologies.

Press Release Summary:



To help reduce time to market for designers of advanced SoCs, high-speed SerDes communication interfaces and low-latency Denali® DDR memory IP solutions support TSMC's 16 nm FinFET Compact (16FFC) and 28 nm HPC Plus (28HPC+) process technologies. Design IP is available for such industry standards as DDR, PCIe, MIPI, Ethernet, USB, DisplayPort, and 802.11.



Original Press Release:



Cadence Design IP to Support TSMC 16FFC and 28HPC+ Process Technologies



SAN JOSE, Calif. – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it is updating its leading-edge, high-speed SerDes communication interfaces and low-latency Denali® DDR memory IP solutions to support TSMC's 16nm FinFET Compact (16FFC) and 28nm HPC Plus (28HPC+) process technologies. These key design IP solutions for TSMC's 16FFC and 28HPC+ processes can help reduce time to market for customers designing advanced Systems-on-Chip (SoCs).



Cadence provides design IP for a wide array of industry standards such as DDR, PCIe, MIPI, Ethernet, USB, DisplayPort, and 802.11. Delivery of IP for 28HPC+ process technology will begin with Denali DDR memory IP in Q2 '16, and IP for the other standards in Q4 '16. Delivery of IP for the 16FFC process will begin with 16Gbps SerDes IP in Q3 '16, and IP for the other standards in Q4 '16. For more information on Cadence's design IP offerings, visit: http://www.cadence.com/news/DIP.



"Our collaboration with TSMC is vital for meeting mutual customer demand for our SerDes and DDR IP using the latest 16nm and 28nm process technologies," said Hugh Durdan, vice president of marketing in the Design IP group at Cadence. "We continue to push the performance envelope with our Denali DDR/LPDDR memory IP and our high-speed SerDes, utilizing the benefits of TSMC's process innovations. The availability of our design IP for 16FFC and 28HPC+ can meet customers' SoC design needs for high-performance memory interface, SerDes interface, and analog IP support."



"Due to the fast adoption rate of both our 16FFC and 28HPC+ processes it is extremely important to have key design IP available," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "TSMC collaborates closely with Cadence to provide the design IP necessary for mutual customers who serve the mainstream market with applications ranging from smartphones and consumer products to enterprise networking, cloud computing and wearables."



About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com/.



© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Denali are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.



For more information, please contact:

Cadence Newsroom

408-944-7039

newsroom@cadence.com



Web Site: http://www.cadence.com

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