Company News

Cadence Design Systems, Inc.

2655 Seely Avenue, San Jose, CA, 95134, USA

  • 408-943-1234

Latest New Product News from
Cadence Design Systems, Inc.

Computer Hardware & Peripherals

Tensilica® Vision C5 DSP IP comes with iDMA and AXI4 interface.

May 05, 2017

Delivering one TeraMAC (TMAC)/sec computational capacity in less than 1mm² silicon area, Tensilica® Vision C5 DSP IP features VLIW SIMD architecture with 128-way, 8-bit SIMD or 64-way 16 bit SIMD. Offering 1024 8-bit MACs or 512 16-bit MACs resolution, unit accelerates... Read More

Cadence® Verification IP Solution is based on PCIe 4.0 specification.

May 04, 2017

Consisting of controller, PHY, software drivers, simulation models and user guides, Cadence® Verification IP Solution supports Xcelium™ Parallel Logic Simulator and third-party simulators. Equipped with Cadence Interconnect Validator for ensuring correctness and completeness of data, CCIX system enables seamless data sharing with speeds up to 25Gbps. Designed with ARM® CoreLink™ CMN-600... Read More

Test & Measuring Instruments

Xcelium™ Parallel Simulator uses multi-core parallel computing technology.

Mar 02, 2017

Enabling customer to achieve 2X improved single-core performance, Xcelium™ Parallel Simulator offers performance speed of 3X for RTL design, 5X for gate-level and 10X for DFT simulations. Unit supports modern design styles and IEEE standards. Xcelium™ comes with SystemVerilog testbench coverage, parallel multi-core build and asperGold® Apps.

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Test & Measuring Instruments

Protium S1 Prototyping Platform features 6X higher design capacity.

Mar 02, 2017

Using Palladium Z1 enterprise emulation, Protium S1 Prototyping Platform provides front-end congruency for easy adoption and fast bring-up. Enhancing memory backdoor access, force and release and runtime control, platform supports System Design Enablement strategy and uses Xilinx® Virtex™ UltraScale™ FPGA technology.

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XJTAG® DFT Assistant for OrCAD® Capture identifies common errors in a JTAG scan chain.

Nov 17, 2016

Enabling engineers detect and rectify PCB errors (JTAG) before production, XJTAG® DFT Assistant for OrCAD® Capture prevents costly reprints and project delays. Containing two key elements: XJTAG Chain Checker identifies common errors in a JTAG scan chain, and XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, DFT allows user to export a preliminary... Read More

Computer Hardware & Peripherals

Cadence RAK for ARM Cortex-M23 and Cortex-M33 processors.

Oct 28, 2016

Creating low-power ARM Cortex-M23 and Cortex-M33 processors, Cadence’s Rapid Adoption Kit address the development of secure IoT rapidly and efficiently. Consisting of end-to-end digital implementation and signoff flow, RAK enables quick silicon delivery of ARM-based applications. Features optimal power, performance and area, fast runtimes and efficient design closures and implementation of IoT... Read More


TSMC's System Design Solution for advanced wafer-level Integrated Fan-Out (InFO) packaging technology.

Oct 13, 2016

With analysis tools that enable concurrent multi-chip optimization for designs using InFO, this design solution includes multiple IC signoff solutions including, the Tempus™ Timing Signoff Solution, the Voltus™-Sigrity Package Analysis that offer multi-die concurrent electro-migration IR drop (EMIR) analysis, and the Cadence Physical Verification System (PVS), which provides DRC and layout... Read More

Electronic Components & Devices

Processor Architecture has optimized floating-point scalability.

Sep 30, 2016

To meet DSP application demands, 12th generation Tensilica® Xtensa® base processor architecture makes technologies available for customization and increases floating-point choices from 2 to 64 FLOPS/cycle. Features include click-box options for Tensilica Vision P6 DSP and Fusion G3 DSP and ConnX BBE DSP support. Additional tools include hardware floating-point ABI for increased... Read More

Test & Measuring Instruments

ARM Cortex-R52 CPU Kit fosters accelerated adoption and use.

Sep 22, 2016

Cadence® RAK (Rapid Adoption Kit) is optimized for ARM® Cortex®-R52 CPU, which targets embedded designs for automotive, medical, and industrial safety applications. Solution, which consists of complete digital implementation and signoff flow, works with ARM Artisan® physical IP to help designers meet challenging PPA (power, performance, and area) goals. Full-flow reference... Read More

Computer Hardware & Peripherals, Electronic Components & Devices

Multi-Purpose DSP targets compute-intensive SoC designs.

Jul 28, 2016

With Xtensa instruction-set architecture, quad 32-bit integer MACs, and quad single-precision 32-bit floating-point MACs, Cadence® Tensilica® Fusion G3 Digital Signal Processor supports compute-intensive applications including radar, imaging, and mid- to high-end audio pre/post-processing. Unit offers comprehensive data-type support with auto-vectorization. DSP provides real-time control... Read More

Computer Hardware & Peripherals, Electronic Components & Devices

Vision DSP targets embedded neural network applications.

May 04, 2016

Based on Cadence Tensilica Xtensa® architecture, Cadence® Tensilica® Vision P6 combines flexible hardware choices with library of vision/imaging DSP functions and applications. Device quadruples multiply-accumulate (MAC) performance compared to previous generation, and utilizes 8- and 16-bit arithmetic to optimize key vision functions such as convolution, FIR filters, and matrix... Read More


IC Packaging Design/Analysis Solution offers all necessary tools.

Mar 21, 2016

Focused on advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs, IC packaging design and analysis solution includes Cadence® OrbitIO™ Interconnect Designer, Cadence System-in-Package (SiP) Layout, and Cadence Physical Verification System (PVS). Capabilities enable multi-substrate interconnect pathway design, refinement, implementation and manufacturing... Read More

Electronic Components & Devices

Design IP supports TSMC 16FFC and 28HPC+ process technologies.

Mar 18, 2016

To help reduce time to market for designers of advanced SoCs, high-speed SerDes communication interfaces and low-latency Denali® DDR memory IP solutions support TSMC's 16 nm FinFET Compact (16FFC) and 28 nm HPC Plus (28HPC+) process technologies. Design IP is available for such industry standards as DDR, PCIe, MIPI, Ethernet, USB, DisplayPort, and 802.11. Read More


Enterprise Emulation Platform offers datacenter-class performance.

Nov 18, 2015

Able to execute up to 2,304 parallel jobs and scale up to 9.2 billion gates, Cadence® Palladium® Z1 has rack-based blade architecture and can be utilized across global design teams to verify complex SoCs. Virtual target relocation capability optimizes utilization, while payload allocation into available resources at run time helps avoid re-compiles. Along with versatility via 12+... Read More

Communication Systems & Equipment, Electrical Equipment & Systems

IP Subsystem integrates USB Type-C, USB power delivery, and more.

Oct 27, 2015

IP subsystem enables development of single-chip solutions for combining video, audio, USB, and up to 100 W of power on one external connector. Mitigating project risk and facilitating SoC integration, pre-verified components include single-chip port controller IP that incorporates USB Type-C™, USB Power Delivery, and DisplayPort™ Alternate Mode (Alt Mode). USB 3.0 xHCI Host and Device... Read More

Mechanical Components and Assemblies

DSP Core enables 4K mobile imaging.

Oct 09, 2015

Designed to off-load vision and imaging functions from main CPU, Cadence® Tensilica® Vision P5 saves energy in image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection, augmented reality, and object tracking applications. Device features 1,024 bit memory interface with SuperGather™ technology; up to 4 vector ALU operations per cycle, each... Read More

Materials & Material Processing, Test & Measuring Instruments

Power Analyzer accelerates accurate early assessments.

Aug 07, 2015

Built on multi-threaded architecture, Cadence® Joules™ RTL Power Solution lets SoC designers analyze power consumption during design exploration. Rapid prototype technology enables this register-transfer level (RTL) power analysis solution to analyze designs of up to 20 million instances with gate-level accuracy within 15% of final power as signed off in Cadence Voltus™ IC Power... Read More

Test & Measuring Instruments

PCB EDA Software makes design cycles shorter and predictable.

May 26, 2015

Promoting efficiency and productivity for PCB designers, Allegro® 16.6 includes Allegro PCB Designer Manufacturing Option that helps streamline development of release-to-manufacturing package for products. Allegro Rules Developer and Checker, also included, offers single source for all design rules checks (DRCs) within PCB, lets users develop custom fabrication and assembly rules, and... Read More


SoC Implementation Software accelerates optimized design delivery.

Mar 18, 2015

Driven by massively parallel architecture, Innovus™ Implementation System helps SoC developers accelerate delivery of designs with optimized power, performance, and area (PPA). Physical implementation solution typically provides 10%–20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10 nm FinFET processes and established process nodes. Features include... Read More

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Cadence Design Systems, Inc.