Cadence Design Systems, Inc.
San Jose, CA 95134
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New 3D Transient Solver Simulating Software Solves Electromagnetic Interference (EMI) System Design Issues
Built on parallel matrix solver technology that handles workload levels to test prototypes for electromagnetic compatibility (EMC) compliance. Can quickly and accurately simulate large and complex hyperscale, automotive, mobile, and aerospace and defense systems. Capable of simulating large designs, reducing respins and accelerating time to market.
Read More »
New Celsius Thermal Solver Simulation Software Uses Matrix Solver Technology
Integrates with Cadence IC, package and PCB implementation platforms that accelerates and simplifies design iterations. Enables system analysis and design insights and empowers electrical design teams to detect and mitigate thermal issues early in design process. Performs both static and dynamic electrical-thermal co-simulations based on actual flow of electrical power in advanced 3D structures,...
Read More »
Cadence Releases JasperGold Formal Verification Platform with Smart Proof Technology
Offered with machine learning technology and core formal technology enhancements. The machine learning helps in selecting and parameterizing solvers to enable first-time proofs. Features improved proof-core accuracy and new technology for deriving coverage from deep bug hunting an formal coverage analysis views.
Read More »Cadence Tools and Flows Achieve Production-Ready Certification for TSMC's 12FFC Process
New technologies enable chip design for emerging mid-range mobility and high-end consumer applications SAN JOSE, Calif., Sept. 11, 2017 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence® digital, signoff and custom/analog tools and flows have achieved v1.0 certification for TSMC's 12nm FinFET Compact (12FFC) process technology and are production ready for customers...
Read More »
Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
Reference flow available for early customer engagement AUSTIN, Texas, June 20, 2017 - DESIGN AUTOMATION CONFERENCE - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom/analog and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40...
Read More »
Tensilica® Vision C5 DSP IP comes with iDMA and AXI4 interface.
Delivering one TeraMAC (TMAC)/sec computational capacity in less than 1mm² silicon area, Tensilica® Vision C5 DSP IP features VLIW SIMD architecture with 128-way, 8-bit SIMD or 64-way 16 bit SIMD. Offering 1024 8-bit MACs or 512 16-bit MACs resolution, unit accelerates neural network computational layers. Suitable for vision, radar/lidar and fused-sensor applications, Vision C5 DSP supports...
Read More »CCIX interface and verification IP solution is based on PCIe 4.0 specification.
Consisting of controller, PHY, software drivers, simulation models and user guides, Cadence® Verification IP Solution supports Xcelium™ Parallel Logic Simulator and third-party simulators. Equipped with Cadence Interconnect Validator for ensuring correctness and completeness of data, CCIX system enables seamless data sharing with speeds up to 25Gbps. Designed with ARM® CoreLink™ CMN-600...
Read More »
Protium S1 Prototyping Platform features 6X higher design capacity.
Using Palladium Z1 enterprise emulation, Protium S1 Prototyping Platform provides front-end congruency for easy adoption and fast bring-up. Enhancing memory backdoor access, force and release and runtime control, platform supports System Design Enablement strategy and uses Xilinx® Virtex™ UltraScale™ FPGA technology.
Read More »Xcelium Parallel Simulator uses multi-core parallel computing technology.
Enabling customer to achieve 2X improved single-core performance, Xcelium™ Parallel Simulator offers performance speed of 3X for RTL design, 5X for gate-level and 10X for DFT simulations. Unit supports modern design styles and IEEE standards. Xcelium™ comes with SystemVerilog testbench coverage, parallel multi-core build and asperGold® Apps.
Read More »XJTAG® DFT Assistant for OrCAD® Capture identifies common errors in a JTAG scan chain.
Enabling engineers detect and rectify PCB errors (JTAG) before production, XJTAG® DFT Assistant for OrCAD® Capture prevents costly reprints and project delays. Containing two key elements: XJTAG Chain Checker identifies common errors in a JTAG scan chain, and XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, DFT allows user to export a preliminary...
Read More »
New 3D Transient Solver Simulating Software Solves Electromagnetic Interference (EMI) System Design Issues
Built on parallel matrix solver technology that handles workload levels to test prototypes for electromagnetic compatibility (EMC) compliance. Can quickly and accurately simulate large and complex hyperscale, automotive, mobile, and aerospace and defense systems. Capable of simulating large designs, reducing respins and accelerating time to market.
Read More »
New Celsius Thermal Solver Simulation Software Uses Matrix Solver Technology
Integrates with Cadence IC, package and PCB implementation platforms that accelerates and simplifies design iterations. Enables system analysis and design insights and empowers electrical design teams to detect and mitigate thermal issues early in design process. Performs both static and dynamic electrical-thermal co-simulations based on actual flow of electrical power in advanced 3D structures,...
Read More »
Cadence Releases JasperGold Formal Verification Platform with Smart Proof Technology
Offered with machine learning technology and core formal technology enhancements. The machine learning helps in selecting and parameterizing solvers to enable first-time proofs. Features improved proof-core accuracy and new technology for deriving coverage from deep bug hunting an formal coverage analysis views.
Read More »Cadence Tools and Flows Achieve Production-Ready Certification for TSMC's 12FFC Process
New technologies enable chip design for emerging mid-range mobility and high-end consumer applications SAN JOSE, Calif., Sept. 11, 2017 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence® digital, signoff and custom/analog tools and flows have achieved v1.0 certification for TSMC's 12nm FinFET Compact (12FFC) process technology and are production ready for customers...
Read More »
Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
Reference flow available for early customer engagement AUSTIN, Texas, June 20, 2017 - DESIGN AUTOMATION CONFERENCE - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom/analog and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40...
Read More »
Tensilica® Vision C5 DSP IP comes with iDMA and AXI4 interface.
Delivering one TeraMAC (TMAC)/sec computational capacity in less than 1mm² silicon area, Tensilica® Vision C5 DSP IP features VLIW SIMD architecture with 128-way, 8-bit SIMD or 64-way 16 bit SIMD. Offering 1024 8-bit MACs or 512 16-bit MACs resolution, unit accelerates neural network computational layers. Suitable for vision, radar/lidar and fused-sensor applications, Vision C5 DSP supports...
Read More »CCIX interface and verification IP solution is based on PCIe 4.0 specification.
Consisting of controller, PHY, software drivers, simulation models and user guides, Cadence® Verification IP Solution supports Xcelium™ Parallel Logic Simulator and third-party simulators. Equipped with Cadence Interconnect Validator for ensuring correctness and completeness of data, CCIX system enables seamless data sharing with speeds up to 25Gbps. Designed with ARM® CoreLink™ CMN-600...
Read More »
Protium S1 Prototyping Platform features 6X higher design capacity.
Using Palladium Z1 enterprise emulation, Protium S1 Prototyping Platform provides front-end congruency for easy adoption and fast bring-up. Enhancing memory backdoor access, force and release and runtime control, platform supports System Design Enablement strategy and uses Xilinx® Virtex™ UltraScale™ FPGA technology.
Read More »Xcelium Parallel Simulator uses multi-core parallel computing technology.
Enabling customer to achieve 2X improved single-core performance, Xcelium™ Parallel Simulator offers performance speed of 3X for RTL design, 5X for gate-level and 10X for DFT simulations. Unit supports modern design styles and IEEE standards. Xcelium™ comes with SystemVerilog testbench coverage, parallel multi-core build and asperGold® Apps.
Read More »XJTAG® DFT Assistant for OrCAD® Capture identifies common errors in a JTAG scan chain.
Enabling engineers detect and rectify PCB errors (JTAG) before production, XJTAG® DFT Assistant for OrCAD® Capture prevents costly reprints and project delays. Containing two key elements: XJTAG Chain Checker identifies common errors in a JTAG scan chain, and XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, DFT allows user to export a preliminary...
Read More »