Cadence Design Systems, Inc.

Computer Hardware & Peripherals

Flexible Processors let users create custom instruction sets.

Blending fixed-architecture solutions with Application Specific Instruction-set Processor tools, TensilicaÂ-® XtensaÂ-® LX6 and Xtensa 11 processors include core Xtensa instruction set architecture. Flexible length instruction extensions for XtensaÂ- LX6 allow very long instruction word (VLIW) instructions from 4–16 bytes. Other features include option for run-time power-down of...

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Computer Hardware & Peripherals

HARMAN Clari-Fi Music Restoration Technology Now Available on Cadence Tensilica HiFi Audio/Voice DSP Family

Solution to be demonstrated at 2015 International Consumer Electronics Show SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that HARMAN's Clari-Fi™ music restoration technology has been ported to the CadenceÂ-® TensilicaÂ-® HiFi Audio/Voice digital signal processor (DSP) family. For more information on Tensilica HiFi Audio/Voice DSPs, visit...

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Computer Hardware & Peripherals

DSP IP Core supports 32-bit audio/voice processing.

Enabling emerging multi-channel object-based audio standards, TensilicaÂ-® HiFi 4 Audio/Voice DSP IP Core is suited for digital TV, set-top box, Blu-ray Disc, and automotive infotainment. Processor supports four 32 x 32-bit multiplier-accumulators per cycle with 72-bit accumulators for computationally intensive functions such as Fast Fourier Transform and finite impulse response. Four very...

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Software

SoC Verifier improves productivity and end product quality.

Intended for use-case, scenario-based software driven system-on-chip (SoC) verification, CadenceÂ-® Perspec™ System Verifier reduces complex test development to days while allowing design teams to reproduce, find, and fix complex bugs. Graphical specification of system-level verification scenarios and definition of SoC topology and actions automates system-level, coverage-driven test...

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Materials

Cadence DDR4 PHY IP Achieves 2667 Mbps Performance - Fastest in the Industry

Highlights: - 2667 Mbps performance provides higher bandwidth - Reduced power for low-cost computing - Greater reliability and improved stacking capabilities SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has achieved 2667 Mbps performance on its DDR4 PHY Intellectual Property (IP) at 28nm, the...

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Software

DesignCon 2014: Get a Sneak Peak of Sigrity 16.63 at Cadence Booth #507

SAN JOSE, Calif.Â- — Cadence Design Systems, Inc. (NASDAQ:CDNS) plans to showcase its AllegroÂ-® SigrityÂ-® solutions for signal integrity and power integrity at DesignCon 2014. Visitors will be the first to see features released in CadenceÂ-® Sigrity 16.63, including new technology supporting analysis and compliance checking of DDR4 interfaces. WHEN: Tuesday, January 28,...

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Electronic Components & Devices

Cadence C-to-Silicon Compiler Helps Renesas Realize Quick HEVC IP Development

SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation shortened its design and verification time by 70 percent by utilizing CadenceÂ-® C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled...

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Software

EDA Software accelerates SoC verification closure.

For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations....

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Software

IC Design Software uses hierarchical design capabilities.

Cadence First Encounter Ultra provides virtual prototyping, physical synthesis, and full-chip hierarchical floor planning and placement. Cadence SoC Encounter front-to-back hierarchical IC implementation provides solutions for large-scale system-on-a-chip (SoC) design with 30-million gate synthesis and place-and-route capability. SoC Encounter partitions chips into smaller blocks to be designed...

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Software

Software Package assures full design verification.

NC-Sim Plus package includes NC-Sim mixed language simulator, which handles ASIC, SoC, and FPGA designs, and Verification Cockpit functional verification tool. It also includes TestBuilder open-source test bench development tool, which is based on C++ language, and includes C++ class libraries with transaction models and functions. Software package with BuildGates(R) synthesis tools is suitable...

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Mergers & Acquisitions

Cadence Completes Acquisition of Rocketick Technologies

SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has completed the acquisition of Rocketick Technologies, Ltd., an Israel-based pioneer and leading provider of multicore parallel simulation. The completion of this transaction strengthens Cadence's System Design Enablement strategy by delivering ultra-high-performance simulation to accelerate the development...

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Computer Hardware & Peripherals

Flexible Processors let users create custom instruction sets.

Blending fixed-architecture solutions with Application Specific Instruction-set Processor tools, TensilicaÂ-® XtensaÂ-® LX6 and Xtensa 11 processors include core Xtensa instruction set architecture. Flexible length instruction extensions for XtensaÂ- LX6 allow very long instruction word (VLIW) instructions from 4–16 bytes. Other features include option for run-time power-down of...

Read More »
Computer Hardware & Peripherals

HARMAN Clari-Fi Music Restoration Technology Now Available on Cadence Tensilica HiFi Audio/Voice DSP Family

Solution to be demonstrated at 2015 International Consumer Electronics Show SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that HARMAN's Clari-Fi™ music restoration technology has been ported to the CadenceÂ-® TensilicaÂ-® HiFi Audio/Voice digital signal processor (DSP) family. For more information on Tensilica HiFi Audio/Voice DSPs, visit...

Read More »
Computer Hardware & Peripherals

DSP IP Core supports 32-bit audio/voice processing.

Enabling emerging multi-channel object-based audio standards, TensilicaÂ-® HiFi 4 Audio/Voice DSP IP Core is suited for digital TV, set-top box, Blu-ray Disc, and automotive infotainment. Processor supports four 32 x 32-bit multiplier-accumulators per cycle with 72-bit accumulators for computationally intensive functions such as Fast Fourier Transform and finite impulse response. Four very...

Read More »
Software

SoC Verifier improves productivity and end product quality.

Intended for use-case, scenario-based software driven system-on-chip (SoC) verification, CadenceÂ-® Perspec™ System Verifier reduces complex test development to days while allowing design teams to reproduce, find, and fix complex bugs. Graphical specification of system-level verification scenarios and definition of SoC topology and actions automates system-level, coverage-driven test...

Read More »
Materials

Cadence DDR4 PHY IP Achieves 2667 Mbps Performance - Fastest in the Industry

Highlights: - 2667 Mbps performance provides higher bandwidth - Reduced power for low-cost computing - Greater reliability and improved stacking capabilities SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has achieved 2667 Mbps performance on its DDR4 PHY Intellectual Property (IP) at 28nm, the...

Read More »
Software

DesignCon 2014: Get a Sneak Peak of Sigrity 16.63 at Cadence Booth #507

SAN JOSE, Calif.Â- — Cadence Design Systems, Inc. (NASDAQ:CDNS) plans to showcase its AllegroÂ-® SigrityÂ-® solutions for signal integrity and power integrity at DesignCon 2014. Visitors will be the first to see features released in CadenceÂ-® Sigrity 16.63, including new technology supporting analysis and compliance checking of DDR4 interfaces. WHEN: Tuesday, January 28,...

Read More »
Electronic Components & Devices

Cadence C-to-Silicon Compiler Helps Renesas Realize Quick HEVC IP Development

SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation shortened its design and verification time by 70 percent by utilizing CadenceÂ-® C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled...

Read More »
Software

EDA Software accelerates SoC verification closure.

For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations....

Read More »
Software

IC Design Software uses hierarchical design capabilities.

Cadence First Encounter Ultra provides virtual prototyping, physical synthesis, and full-chip hierarchical floor planning and placement. Cadence SoC Encounter front-to-back hierarchical IC implementation provides solutions for large-scale system-on-a-chip (SoC) design with 30-million gate synthesis and place-and-route capability. SoC Encounter partitions chips into smaller blocks to be designed...

Read More »

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