Clock IC harnesses GPS signals for synchronization.
Press Release Summary:
Leveraging AD9548, system designers can use standard 1 pps (pulse-per-second) signal of GPS satellite transmitters to generate and synchronize clock signals for communications infrastructure equipment. Clock distribution section provides 4 output drivers, each programmable as single differential LVPECL/LVDS output or pairs of single-ended CMOS outputs. Other features include reference clock multiplier, digitally-controlled loop filter, and manual/automatic holdover circuitry.
Original Press Release:
Clock IC First to Harness GPS Signals for Synchronization
- ADI's AD9548 taps ubiquitous GPS signals as a timing base; replaces multi-chip clocks with an accurate, highly integrated alternative for cable, optical networks and wireless base stations.
Norwood, MA (06/11/2009) - Analog Devices, Inc. (ADI), a global leader in high-performance signal processing, introduced today the industry's first clock IC that enables system designers to use the standard, readily available and free 1-pps (pulse-per-second) signal of GPS (global positioning system) satellite transmitters to generate and synchronize clock signals for communications infrastructure equipment.
Developed for remote optical and wireless network nodes, cable infrastructure and data communications equipment, the AD9548 clock generator/synchronizer eliminates the dedicated oscillators, phase-locked loops, and other clock recovery circuitry communications systems previously required to generate clock signals synchronized to the widely available 1-pps GPS standard. Using the AD9548 to leverage GPS signals simplifies and shortens the design process while providing a lower-power timing reference.
The AD9548 includes a digital PLL that up-converts the 1-pps GPS signal while reducing input-time jitter or phase noise associated with the external references to as little as 300 femto seconds. The clock distribution section provides four output drivers. Each driver is programmable either as a single differential LVPECL/LVDS (low-voltage positive emitter-coupled logic/low-voltage differential signaling) output or as pairs of single-ended CMOS (complementary metal-oxide semiconductor) outputs. Each of the four outputs has a dedicated 30-bit programmable post divider enabling the generation of multiple different output frequencies. An integrated reference clock multiplier allows for system clock references as low as 4 MHz while still supporting outputs of up to 450 MHz. The AD9548 also includes a digitally-controlled loop filter programmable to as low as 1mHz (1x10-3), as well as manual and automatic holdover circuitry that continuously generates a low jitter, valid output clock even when some, or all, references have failed.
Pricing, Availability and Complementary Components
Product Availability Price Each per 1,000 Temperature Range Packaging
AD9548 Now $24.82 -40°C to +85°C 88-lead LFCSP
Complementary components include ADI clock buffers, including the ADCLK854 LVDS/CMOS and ADCLK846 LVDS clock buffers, as well as the ADCLK954 and ADCLK946. The recently announced AD9356 and AD9357 transceivers also work well with the AD9548.
For more information, visit www.analog.com/pr/AD9548. For product information on ADI's additional clock and timing offerings, visit http://www.analog.com/clock-and-timing.
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