Xilinx Announces FPGA-Based Deserializer Solution for TI's ADS6000 ADC Family

SAN JOSE, Calif., April 16 -- Xilinx, Inc. (NASDAQ:XLNX), today announced immediate availability of a Virtex(TM)-4 FPGA-based deserializer reference design, application note and evaluation module jointly developed with Texas Instruments. The new reference design, together with the accompanying application note, deserializes data streams from TI's ADS6000 analog-to-digital converter (ADC) family, providing designers a quick and easy solution with which to deploy products based on the latest advanced ADC device technology. The evaluation module, available through TI (TSW1200EVM), consists of a circuit board and a set of preconfigured design files, which enable designers to prototype and evaluate the performance of the latest high-speed ADCs featuring serialized LVDS outputs.

Systems designers can now leverage the enormous serial-to-parallel processing capabilities and programmability of Xilinx Virtex-4 FPGAs to accelerate operations for specialized, high-performance functions. The ability to achieve much higher levels of overall system performance is especially important for multi-channel systems in applications such as broadcast, medical, instrumentation and wireless infrastructure.

"The use of Xilinx Virtex-4 FPGA technology and its ISERDES feature, in combination with excellent support, allowed our design team to meet an extremely aggressive time-to-market window to provide a comprehensive evaluation module that will ultimately reduce cost and development time for our customers," said Heinz-Peter Beckemeyer, general manager, High-Speed ADCs, Texas Instruments.

"Today's announcement represents yet another milestone in our ongoing collaboration with TI to successfully interface our FPGAs to their high-speed ADCs and DAC products," said David Gamba, director of Vertical Market and Partnerships at Xilinx. "By combining TI's leading ADC technology with the programmability and industry-leading high-speed serial performance of our Virtex-4 FPGAs, designers can leverage the evaluation module as a flexible and rapid prototyping environment for designing digital circuits that directly interface to the ADCs."

High-Performance LVDS Interface

Built on the Virtex-4 LX25 platform, the Xilinx deserializer reference design accepts up to four simultaneous ADC channels and provides automatic de- skew and clock alignment functions. Each ADC output is serialized and transmitted through a separate LVDS serial pair. An independent frame clock and serial data clock are provided to allow for easy deserialization. The Xilinx reference design exploits the unique ISERDES dedicated logic in the I/O of the Virtex-4 devices to provide the necessary timing to accept these extremely fast input signals and translate into parallel output busses, which can be more easily integrated.

The serial LVDS interface provides several distinct benefits to the system designer. The lower pin count, both on the ADC and the FPGA, results in less routing lines, potentially fewer board layers, better immunity to external noise and extremely low crosstalk and injection of noise into the printed circuit board. These advantages translate directly into lower system costs and improved system reliability when compared to legacy ADC communication interface technology.

About TI's ADS6000 Data Converters

The pin-compatible ADS6000 family consists of dual- and quad-channel, 12- and 14-bit ADCs at speeds of 80, 100, 125 MSPS (mega samples per second) to provide a simple upgrade path for customers designing communications, instrumentation and imaging products. The ADS6000 family features excellent signal-to-noise ratio of 73.2dB dBFS (70.3dBFS for the 12-bit family) with 83dBc of spurious free dynamic range at 50 MHZ input frequency while only consuming 420mW of power per channel at 125 MSPS (330mW/channel at 80 MSPS). The devices allow high system density for multi-channel applications. Visit www.ti.com/ads6425 for more details as well as pricing and availability information.

When combined with the ADS6000 family of ADC products, the TSW1200EVM allows for easy deserialization and offers a flexible evaluation environment for analysis. The EVM can be connected to a logic analyzer for data analysis or to TI's TSW1100, a high-speed CMOS data capture and analysis tool.

About Xilinx Virtex-4 FPGAs

With more than 100 technical innovations, the Xilinx Virtex-4 family consists of 17 devices and three domain-optimized platforms; Virtex-4 LX FPGAs optimized for logic-intensive designs, Virtex-4 FX FPGAs optimized for high- speed serial connectivity and embedded processing, and Virtex-4 SX FPGAs optimized for high-performance signal processing. For more information on the Virtex-4 product family, visit xilinx.com/virtex4 .

Shipping since May 2006, the newest Virtex-5 family represents the fifth generation Virtex FPGAs. Built on the industry's most advanced 65nm triple- oxide technology, breakthrough new ExpressFabric(TM) technology, and proven ASMBL(TM) architecture, the Virtex-5 FPGA family offers an optimized balance of high-performance, low-power and capabilities. For more information visit www.xilinx.com/ .

Pricing and Availability

The reference design (including VHDL code and test files) and application note are available free of charge from the Xilinx website at xilinx.com/bvdocs/appnotes/xapp866.pdf . The TSW1200EVM high-speed ADC LVDS evaluation module can be purchased directly through TI and its distributors for USD $649.

About Xilinx

Xilinx, Inc. is the worldwide leader of programmable logic solutions. For more information, visit www.xilinx.com/ .

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