Cadence Design Systems, Inc.

Materials

DDR4 PHY IP targets microserver market.

Built on 16 nm FinFET process, Cadence® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers...

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Materials

Cadence Announces Immediate Availability of Industry's First Verification IP for PCI Express 4.0 Technology

Support for next-generation PCI Express architecture enables faster completion of functional verification of SoC designs SAN JOSE, Calif. -- Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced the availability of the industry's first verification IP (VIP) supporting PCI Express® (PCIe®) 4.0 architecture. This VIP enables designers to quickly...

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Software

Cadence Digital and Custom/Analog Tools Achieve TSMC V1.0 DRM Certification for 16nm FinFET Process

Full certification enables customers to tape out 16nm FinFET designs using Cadence tools SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its digital, custom and signoff tools have received V1.0 Design Rule Manual (DRM) and SPICE certification for TSMC's 16nm FinFET process, enabling joint customers to begin...

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Agricultural & Farming Products

Cadence and GLOBALFOUNDRIES Announce First Test Chip Featuring ARM Cortex-A12 Processor in 28nm-SLP Process

Highlights: - Test chip designed to demonstrate performance and power characteristics of ARM® Cortex®-A12 processor on GLOBALFOUNDRIES' 28nm-SLP process - Achieved maximum frequency of 2.0GHz in 15 weeks using the full Cadence RTL-to-GDSII digital implementation and signoff solutions - Full suite of Cadence signoff tools used, including QRC Extraction, Tempus Timing Signoff Solution...

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Software

EDA Software accelerates timing closure of PCB interfaces.

Available within Cadence® Allegro PCB Designer, Allegro® TimingVision™ uses embedded timing engine to analyze entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on canvas. When combined with Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in...

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Communication Systems & Equipment

Global Navigation Satellite Receiver From Galileo Satellite Navigation Now Available on Cadence Tensilica ConnX DSP IP Cores

Demonstration available at the 2014 Mobile World Congress BARCELONA, Spain, -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, and Galileo Satellite Navigation, Ltd. (GSN), a developer of multi-system Global Navigation Satellite System (GNSS) products including software receiver technology, today announced that Galileo's software-based GNSS receiver...

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Materials

Imaging/Video Dataplane Processor handles complex functions.

Tensilica® Imaging and Video Processor-Enhanced Performance (IVP-EP) core is available asÂ- configurable core and complete, pre-built subsystem. Integrating DMA transfer engine with up to 10 GBps throughput and local memory throughput of 1,024 bits per cycle, 4-way VLIW architecture delivers parallelism intermixed with code-compact instructions, with 32-way vector SIMD dataset....

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Computer Hardware & Peripherals

Cadence and Sensory Reduce Voice Activation Power Dissipation in Mobile Devices to Less than 17 MicroWatts

HiFi Mini Running Sensory TrulyHandsfree Voice Activation Solution Now Uses 33 Percent Less Power SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, and Sensory today announced that they have further lowered the power consumption of their industry-leading, ultra-low power DSP-based voice activation solution, which is an ideal...

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Computer Hardware & Peripherals

Baseband DSP IP Cores are optimized for low-power applications.

Respectively, Tensilica® ConnX BBE32EP and BBE64EP are 32- and 64-MAC baseband DSP IP cores optimized for complex number processing at low power. Products excel at processing algorithms for LTE, LTE-Advanced, 802.11ac, HDTV demodulation, 3G/HSPA+, and WiFi (including MIMO processing). Supporting power consumption levels that reduce need for hardware accelerators, cores suit such...

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Services

Cadence Showcases System Development Solutions for Advanced Driver Assistance Systems at Embedded World 2014

FELDKIRCHEN, GermanyÂ- – At this year's embedded world Exhibition &Conference, visitors to Cadence Design Systems, Inc. (NASDAQ: CDNS) booth can learn about early software development, hardware/software integration and co-verification of embedded subsystems. The Cadence® System Development Suite enables accelerated system integration, validation, and bring-up for concurrent...

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