Cadence Design Systems, Inc.

Materials

Cadence DDR4 PHY IP Achieves 2667 Mbps Performance - Fastest in the Industry

Highlights: - 2667 Mbps performance provides higher bandwidth - Reduced power for low-cost computing - Greater reliability and improved stacking capabilities SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has achieved 2667 Mbps performance on its DDR4 PHY Intellectual Property (IP) at 28nm, the...

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Software

DesignCon 2014: Get a Sneak Peak of Sigrity 16.63 at Cadence Booth #507

SAN JOSE, Calif.Â- — Cadence Design Systems, Inc. (NASDAQ:CDNS) plans to showcase its Allegro® Sigrity® solutions for signal integrity and power integrity at DesignCon 2014. Visitors will be the first to see features released in Cadence® Sigrity 16.63, including new technology supporting analysis and compliance checking of DDR4 interfaces. WHEN: Tuesday, January 28,...

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Electronic Components & Devices

Cadence C-to-Silicon Compiler Helps Renesas Realize Quick HEVC IP Development

SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation shortened its design and verification time by 70 percent by utilizing Cadence® C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled...

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Software

EDA Software accelerates SoC verification closure.

For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations....

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Software

UMC Foundry Design Kit for New Cadence Virtuoso Platform Speeds Production of 65nm Designs

December 3, 2007 Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and UMC (NYSE: UMC) (TWSE: 2303), a leading global semiconductor foundry, today announced the availability of UMC 65-nanometer Foundry Design Kits (FDKs) for the latest Cadence® Virtuoso® custom design platform (IC 6.1) release. The kits will be available for designers...

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Software

Software facilitates design of nanometer wireless chips.

Virtuoso® Passive Component Designer delivers complete flow for design, analysis, and modeling of inductors, transformers, and transmission lines. Optimized for 90 and 65 nm process nodes, solution supports advanced design rules and CMP constraints such as dummy metal fills and slotting. Modeling capability converts S-parameter files into physical lumped element models ready for RF...

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Software

IC Design Software uses hierarchical design capabilities.

Cadence First Encounter Ultra provides virtual prototyping, physical synthesis, and full-chip hierarchical floor planning and placement. Cadence SoC Encounter front-to-back hierarchical IC implementation provides solutions for large-scale system-on-a-chip (SoC) design with 30-million gate synthesis and place-and-route capability. SoC Encounter partitions chips into smaller blocks to be designed...

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Software

Software Package assures full design verification.

NC-Sim Plus package includes NC-Sim mixed language simulator, which handles ASIC, SoC, and FPGA designs, and Verification Cockpit functional verification tool. It also includes TestBuilder open-source test bench development tool, which is based on C++ language, and includes C++ class libraries with transaction models and functions. Software package with BuildGates(R) synthesis tools is suitable...

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Computer Hardware & Peripherals

Design System provides hierarchical access to parameters.

SPW 4.8 Signal Processing Worksystem block diagram design solution allows hardware, software, and RF engineers to collaborate on projects. Links with other tools include integrations with Xilinx Coregen solution, with analog design flow that supports Cadence(R) AMS Designer, and with SystemC 2.0. SPW 4.8 users can enter and simulate designs consisting of various types of models including C, C++,...

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