Real Intent Inc
Sunnyvale, CA 94085
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Software provides timing closure verification.
With ability to plug holes in timing closure for electronic design, EnVision TCV(TM) features Meridian(TM) that verifies data traversing asynchronous clock domains on ASIC, SOC, or FPGA devices. Meridian also verifies structure and protocols needed for clock domain crossing safe design and pinpoints design problems with minimum amount of manual sign-off. PureTime feature removes risk of errors in...
Read More »SimPortal Option for Formal Verification & Simulation from Real Intent, Request for Date Meeting
Sunnyvale, California -- February 22, 2006 -- Real Intent, Inc., the leading supplier of formal verification software for electronic design, announced a significant extension of the capabilities of its industry's leading clock tool, Clock Intent Verification(TM). These capabilities include vastly improved design navigation and debug, as well as add an option linking the best of static and dynamic...
Read More »Formal Verification Software targets semiconductor industry.
Built upon single unified database, Verix v5.0 utilizes power of formal analysis to verify design assertions and prove them correct or detect bugs. Convergence Engine core provides Adaptive Orchestration, which offers algorithm for deliberating proof between multiple solvers to create solution in most optimal manner. Two-Dimensional Compression combats state space explosion by compressing natural...
Read More »ABV Software supports Accellera's PSL standard.
Verix(TM) v4.3 assertion-based formal verification system ensures that design is free from complex, corner case errors that are hard to catch in simulations. Support of PSL provides concise language for assertion specification and functional modeling. As interoperable specification language, it allows designers to use same assertions to drive both simulation and formal verification methodologies...
Read More »Real Intent Reports Stellar Revenue Growth of over 80% in 2010
SUNNYVALE, California - January 25, 2011 - Real Intent, Inc., the leader in automating the intelligence of formal techniques for design verification signoff, announced today that the company's revenue in 2010 increased more than 80% when compared to 2009. In addition, the company's customer list grew by over 50%, adding major semiconductor companies in storage, computing, networking,...
Read More »Real Intent Reports Success; Revenue Increased 76%
Interest in Verification Solutions That Improve Design Quality Continues to Grow SUNNYVALE, California - August 11, 2010 - Real Intent Inc., the innovator in automating the intelligence of formal techniques for design verification, announced today that revenue for the first half of 2010 was up 76% when compared to the same period last year, and the company is on track, in its 11th year of...
Read More »
Software provides timing closure verification.
With ability to plug holes in timing closure for electronic design, EnVision TCV(TM) features Meridian(TM) that verifies data traversing asynchronous clock domains on ASIC, SOC, or FPGA devices. Meridian also verifies structure and protocols needed for clock domain crossing safe design and pinpoints design problems with minimum amount of manual sign-off. PureTime feature removes risk of errors in...
Read More »SimPortal Option for Formal Verification & Simulation from Real Intent, Request for Date Meeting
Sunnyvale, California -- February 22, 2006 -- Real Intent, Inc., the leading supplier of formal verification software for electronic design, announced a significant extension of the capabilities of its industry's leading clock tool, Clock Intent Verification(TM). These capabilities include vastly improved design navigation and debug, as well as add an option linking the best of static and dynamic...
Read More »Formal Verification Software targets semiconductor industry.
Built upon single unified database, Verix v5.0 utilizes power of formal analysis to verify design assertions and prove them correct or detect bugs. Convergence Engine core provides Adaptive Orchestration, which offers algorithm for deliberating proof between multiple solvers to create solution in most optimal manner. Two-Dimensional Compression combats state space explosion by compressing natural...
Read More »ABV Software supports Accellera's PSL standard.
Verix(TM) v4.3 assertion-based formal verification system ensures that design is free from complex, corner case errors that are hard to catch in simulations. Support of PSL provides concise language for assertion specification and functional modeling. As interoperable specification language, it allows designers to use same assertions to drive both simulation and formal verification methodologies...
Read More »