Multi-Protocol IP fosters DDR4/LPDDR4 migration sans redesign.
Press Release Summary:
Scalable up to 3,200 Mbps, Cadence® DDR controller and PHY IP enables designers to take advantage of higher performance DDR4 and LPDDR4 DRAMs, when they become available, without requiring systems on chip (SoC) redesign. Single multi-protocol IP solution lets designers address changing memory requirements in consumer, mobile, and enterprise applications.
Original Press Release:
Cadence Announces Industry's First Multi-Protocol DDR4 and LPDDR4 IP Solution
- Multi-protocol DDR4/LPDDR4 controller and PHY IP solution enables designers to make performance and system cost tradeoffs while reducing risk and shortening design cycles
- Combined high-performance and low-power multi-protocol DDR IP provides flexibility to address emerging memory and system cost requirements in consumer, mobile and enterprise applications
- Extends memory leadership from LPDDR3/DDR4/3 to include LPDDR4 with performance up to 3200Mbps
SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the industry's first multi-protocol DDR4 and LPDDR4 intellectual property (IP) Solution. The Cadence® DDR controller and PHY IP can scale up to 3200Mbps, which provides flexibility for designers to easily take advantage of higher performance DDR4 and LPDDR4 DRAMs when they become available, without having to redesign their systems on chip (SoCs).
With a single, multi-protocol IP, designers can easily address changing memory and system cost requirements in consumer, mobile and enterprise applications. They can select the optimal DRAM subsystem implementation for their specific application after the SoC has already been designed.
DDR4 is primarily used in enterprise applications requiring high-capacity and high-reliability DRAM subsystems. LPDDR4 meets the power/performance requirements of mobile applications. Consumer applications, on the other hand, have traditionally used DDR3 DRAMs, moving to DDR4 to benefit from DRAM commodity pricing. Over time, performance requirements for these application areas are currently expected to grow, while performance levels for LPDDR4 are expected to improve. With the new IP, designers can easily migrate from DDR4 to LPDDR4 without a chip redesign.
"The Cadence DDR PHY IP offers high performance, high configurability and flexibility critical to our networking SoC designs," said Gaurav Singh, vice president technical strategy at Applied Micro Circuits Corporation. "With access to the next-generation protocol and having additional flexibility between DDR and LPDDR, Cadence is allowing us to further innovate and provide greater differentiation and value to our customers."
"For the first time, high performance mobile, consumer and enterprise application requirements can be addressed in a single DDR IP solution," said Martin Lund, senior vice president of the IP Group at Cadence. "By using the Cadence multi-protocol DDR IP, we believe our customers can have more confidence that their products can meet memory subsystem requirements, allowing them to optimize for performance, power and density in their end system."
Availability
The new Cadence multi-protocol DDR IP solution is available now for early adopters, with general availability currently scheduled for Q4 of 2014. To learn more about this product, click here.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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