EDA Software accelerates SoC verification closure.
Press Release Summary:
For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations. Support for SystemVerilog IEEE 1800-2012 real number modeling enables faster mixed-signal simulation.
Original Press Release:
Cadence Incisive 13.2 Platform Sets New Standard for SoC Verification Performance and Productivity
SAN JOSE, Calif., -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced a new version of the Incisive® functional verification platform, once again setting a new standard for overall verification performance and productivity. Addressing both intellectual property (IP) block-to-chip and system-on-chip (SoC) verification challenges, the Incisive 13.2 platform offers orders of magnitude faster performance with two new engines and additional automation features to speed SoC verification closure.
For IP block-to-chip verification, enhancements include:
--Â New Trident engine in the Incisive Formal Verifier and the Incisive Enterprise Verifier, which improves formal analysis performance up to 20X
-- New constraint engine in the Incisive Enterprise Simulator that speeds UVM and SystemVerilog testbench simulation, and simulation acceleration with the Palladium® platform by up to 10X
--Â New SystemVerilog support in Incisive Debug Analyzer plus unique UVM debug capabilities and optimized probing in the SimVision debug environment inside Incisive Enterprise Simulator that reduces database size up to 10X
--Â New IEEE 1647 e unit testing without simulation, reducing debug time for testbench code by 30%
For SoC verification, enhancements include:
--Â Comprehensive x-propagation support in the Incisive Enterprise Simulator and the Incisive Enterprise Verifier to speed SoC reset and low-power simulations up to 5X
--Â New support for SystemVerilog IEEE 1800-2012 real number modeling in the Incisive Digital Mixed Signal option for faster mixed-signal simulation over 100X.
"Verification is a growing challenge that we have to address with a finite amount of resources," said Chan Lee, vice president of engineering at Ambarella, Inc. "We adopted the X-propagation support during 2013 to speed our reset simulation performance significantly. The additional automation provided by the Incisive verification platform helps us increase our verification productivity."
The complete list of key performance enhancements and productivity features can be found here.
"Verification engineers are pressed for time and need strong verification performance. Incisive 13.2 delivers this but also goes beyond raw clocks per second to encompass capabilities from formal apps, debug, and metric aggregation in order to speed verification closure. The combination of automation and integration provides our customers with real gains to ease the challenges of SoC verification," said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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Cadence Design Systems, Inc.
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