Product News: Mechanical Components and Assemblies
DDR4 PHY IP targets microserver market.
Press Release Summary:
May 28, 2014 - Built on 16 nm FinFET process, CadenceÂ® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize maximum performance of DDR4 standard, which is specified to scale up to 3,200 Mbps.
Original Press Release
Cadence Offers Immediate Availability of DDR4 PHY IP on TSMC 16nm FinFET Process
Press release date: May 19, 2014
The Cadence DDR4 PHY IP supports an unbuffered dual in-line memory module (UDIMM)/ registered dual in-line memory module (RDIMM) with reliability, availability, and serviceability (RAS) features such as cyclic redundancy check (CRC) and data bus inversion (DBI). The new DDR4 PHY IP implements architectural innovations such as 4X clocking to minimize duty cycle distortion, multi-band power isolation for increased noise immunity, and I/O with slew rate control. The Cadence DDR4 PHY IP together with Cadence DDR4 controller are verified in silicon from TSMC's 16nm FinFET process.
"The demand for 16nm FinFET-based designs continues to grow and is driving the market need for a complementary DDR4 IP offering," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Because we have worked very early and closely with Cadence on this technology, our customers can review the design's silicon results to feel confident about turning to Cadence for comprehensive 16nm support from tools to IP."
"Many of our customers are concerned that their next-generation designs might not reach their performance goals because of the bottleneck in memory systems," stated Martin Lund, Cadence's senior vice president and general manager of the IP Group. "By using Cadence DDR4 IP, we believe our customers can have more confidence that their products will work with future DRAMs designed for higher speeds."
DDR4 PHY IP is silicon-tested and available now. For more information on DDR IP, please visit http://ip.cadence.com/knowledgecenter/customize-main/ddr4-16ff
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