Imaging/Video Dataplane Processor handles complex functions.
February 27, 2014 -
Tensilica® Imaging and Video Processor-Enhanced Performance (IVP-EP) core is available as configurable core and complete, pre-built subsystem. Integrating DMA transfer engine with up to 10 GBps throughput and local memory throughput of 1,024 bits per cycle, 4-way VLIW architecture delivers parallelism intermixed with code-compact instructions, with 32-way vector SIMD dataset. Imaging-specific operations accelerate 8-, 16-, and 32-bit pixel data types and video operation patterns.
|Original Press Release |
Cadence Design Systems, Inc.
2655 Seely Ave.
San Jose, CA, 95134
Cadence Announces New Tensilica Imaging and Video Processor for Increasingly Complex Signal Processing Functions
- 4X better performance than previous IVP core
- Efficient processor-based architecture
- Ideal for camera image processing, video post processing, gesture recognition, automotive driver assistance and computer vision applications
SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced the Tensilica® Imaging and Video Processor-Enhanced Performance (IVP-EP) core, the latest imaging and video dataplane processor in the IVP product line. Ideal for camera image processing, video post processing, gesture recognition, automotive driver assistance and computer vision applications, the IVP-EP core is based on a new, optimized architecture and is available both as a configurable core as well as a complete pre-built subsystem for easier integration into SoCs.
Compared to its predecessor, the IVP-EP processor gives customers up to 4X better performance for applications such as face detection, gesture recognition, augmented reality, video stabilization, high dynamic range (HDR) photos, HDR video, tracking, digital zoom, automotive lane departure, object detection and other imaging and video applications. This enables sustained, complex video processing that cannot be achieved by other general-purpose CPU or GPU processors, with sufficiently low power dissipation for use in smartphones, tablets and other mobile devices. The IVP-EP core is scheduled to be available in May 2014.
"Mobile imaging algorithms demand extreme performance and power efficiency, as there is a high demand for better photos or videos as well as real-time image and video processing," said Jack Guedj, Corporate VP, Intellectual Property Group, Cadence. "We are moving quickly to offer increasingly flexible and higher performance imaging dataplane processor IP to keep up with the high-performance vision applications demanded by leading camera systems while also striving to deliver these solutions at much lower power than what was possible before."
Efficient Processor-Based Architecture
The Cadence Tensilica IVP product line is based on a 4-way VLIW (very long instruction word) architecture that delivers high parallelism intermixed with code-compact instructions, with a 32-way vector SIMD (single instruction, multiple data) dataset. The architecture includes an integrated DMA (direct memory access) transfer engine with up to 10GBps of throughput and local memory throughput of 1024 bits per cycle (64 16-bit pixels/cycle) to keep up with the rapid pace of resolution and frame rate requirements. The IVP-EP also features many imaging-specific operations to accelerate 8-, 16- and 32-bit pixel data types and video operation patterns.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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