ThomasNet News Logo
Sign Up | Log In | ThomasNet Home | Promote Your Business

How to do At-Speed Functional Verification of Serial Interfaces without Functional Software is Described in New eBook

Print | 
Email |  Comment   Share  

Asset InterTech Inc.
2201 N. Central Expy Ste. 105
Richardson, TX, 75080
USA



Press release date: March 11, 2014

Richardson, TX  – Historically, verifying the at-speed functionality of serial interfaces on prototype circuit boards has required the system’s functional software. But the functional software is often not ready yet when prototypes arrive. That means delaying the product’s migration into manufacturing.

A new eBook published by ASSET® InterTech (www.asset-intertech.com) describes how a board bring-up team can use boundary-scan (JTAG), an on-board FPGA and an embedded instrument to test and verify serial interfaces like UART, SPI, I2C and others. ASSET is the leading supplier of debug, validation and test tools.

“When first prototypes for a new design arrive, you want to start wringing them out right away,” said Kent Zetterberg, an ASSET product manager and author of the new eBook. “The last thing the board bring-up team wants to do is wait for the functional software to be completed. We wrote this eBook so engineers would realize they can avoid these sorts of delays. Another good thing about this method is the embedded instrument can be re-used on other designs. So the methodology is easily replicated.”

Titled “Serial Port Functional Test with FPGA UART IP and JTAG,” the new eBook is available for downloading from the eResources center on the ASSET website at: http://www.asset-intertech.com/
Products/Boundary-Scan-Test/BST-Software/
Serial-Port-FPGA-UART-IP-Functional-Test-JTAG


Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from the ASSET website at: http://www.asset-intertech.com/eResources

About ASSET InterTech

ASSET InterTech is a leading supplier to the electronics industry of tools based on embedded instrumentation. Its SourcePoint debugger and the ScanWorks platform for embedded instruments overcome the limitations of external test and measurement equipment by applying instrumentation embedded in code and semiconductors to debug and validate software and firmware, and to perform design validation and manufacturing test on chips and circuit boards. ASSET’s recent acquisition of Arium (www.arium.com) added a powerful suite of firmware debug and trace tools to the ScanWorks platform. Designers can quickly debug firmware and then diagnose how it interacts with hardware. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

Follow us on:
Facebook: https://www.facebook.com/ASSETInterTech
LinkedIn: http://www.linkedin.com/company/asset-intertech-inc.
Twitter: https://twitter.com/ASSETInterTech
YouTube: http://www.youtube.com/ASSETInterTech
Blog:  http://blog.asset-intertech.com/

ASSET and ScanWorks are registered trademarks and Arium and SourcePoint are trademarks of ASSET InterTech, Inc.
Print | 
Email |  Comment   Share  
Contacts: View detailed contact information.


 

Post a comment about this story

Name:
E-mail:
(your e-mail address will not be posted)
Comment title:
Comment:
To submit comment, enter the security code shown below and press 'Post Comment'.
 



 More New Product News from this company:
Software Tools accelerate µC/OS - II code debugging.
Software Debugger accelerates ARM System Trace Macrocell.
Debugging Software fixes code running on ARM cores.
Software Debugger supports microarchitecture with RTIT.
Debugging Tools target ARM code in TI KeyStone II architecture.
More ....
| Featured Manufacturing Jobs
 Other News from this company:
ASSET and SoftIron Collaborate on Rapid Debugging for 64-bit ARM-Based Enterprise Servers using AppliedMicro's X-Gene Technology
Board Test and Debug Security via JTAG, IJTAG is Explored in New eBook
ASSET and Synopsys Collaborate on Proof-of-Concept Demonstrating an IEEE P1687 IJTAG Tools Flow
System Marginality Validation Explained in New eBook By ASSET InterTech
New eBook Explains Faster Parallel Programming of Memories via JTAG on Manufacturing Lines
More ....
 Tools for you
Watch Company 
View Company Profile
Company web site
More news from this company
E-mail this story to a friend
Save Story


Home  |  My ThomasNet News®  |  Industry Market Trends®  |  Submit Release  |  Advertise  |  Contact News  |  About Us
Brought to you by Thomasnet.com        Browse ThomasNet Directory

Copyright © 2014 Thomas Publishing Company. All Rights Reserved.
Terms of Use - Privacy Policy



Error close

Please enter a valid email address