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DesignCon 2014: Get a Sneak Peak of Sigrity 16.63 at Cadence Booth #507

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Cadence Design Systems, Inc.
2655 Seely Ave.
San Jose, CA, 95134

Press release date: January 15, 2014

SAN JOSE, Calif. — Cadence Design Systems, Inc. (NASDAQ:CDNS) plans to showcase its Allegro® Sigrity® solutions for signal integrity and power integrity at DesignCon 2014. Visitors will be the first to see features released in Cadence® Sigrity 16.63, including new technology supporting analysis and compliance checking of DDR4 interfaces.

Tuesday, January 28, through Friday, January 31, 2014

Santa Clara Convention Center

5001 Great America Pkwy

Santa Clara, CA 95054

Booth # 507

The following technologies are scheduled for demonstrations at the show:

-  Constraint-driven power integrity design and analysis
-  Power-aware memory interface design and analysis
-  Multi-gigabit serial link design and analysis
-  Chip-package-board co-analysis

Also, the following Cadence speaker sessions will take place:

•  Panel: System-Level Power Integrity: Tools Providers and Tool Users
-  Session Code: 11-WE7
-  Cadence speaker: Brad Brim
-  Location: Ballroom G
-  Date: Wednesday, January 29
-  Time: 3:45pm-5:00pm

•  Paper: Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems
-  Session Code: 4-TH3
-  Cadence speaker: Brad Brim
-  Location: Ballroom F
-  Date: Thursday, January 30
-  Time: 10:15am-10:55am

•  Panel: Post-Equalization Metrics at 25Gbps and Beyond
-  Session Code: 8-TH7
-  Cadence speaker: Ken Willis
-  Location: Ballroom F
-  Date: Thursday, January 30
-  Time: 3:45pm-5:00pm

•  Paper: Advanced Power-Aware Buffer Behavior Model with Overclocking Solution
-  Session Code: 4-FR3
-  Cadence speaker: Joy Li
-  Location: Ballroom F
-  Date: Friday, January 31
-  Time: 10:40am-11:20am

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Allegro, Sigrity and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries.  All other trademarks are the property of their respective owners.

For more information, please contact:

Cadence Newsroom

Cadence Design Systems, Inc.

Web Site:

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