TestBenching Software simplifies random transaction generation.
Press Release Summary:
VHDL and Verilog system-level testbench generation software, TestBencher Pro, aids creation and application of random bus transactions to RTL and gate-level models. It also facilitates creation of testbenches that reside in different compiled library from design being tested. In addition to graphical HDL debugger with support of ModelSim and Incisive simulators on Windows® and Linux platforms, features include HDL code-free uniform transactor weightings development.
Original Press Release:
SynaptiCAD's TestBencher Simplifies Random Transaction Generation
SynaptiCAD has released a new version of TestBencher Pro, a VHDL and Verilog system-level testbench generation software that dramatically simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The new version also simplfies creation of testbenches that reside in a different compiled library from the design being tested. TestBencher includes an updated version of SynaptiCAD's graphical HDL debugger, BugHunter Pro, with new debugging features and improved support of ModelSim and Incisive simulators on Windows and Linux platforms.
For more information on TestBencher Pro see the TestBencher www.syncad.com/testbencher_verilog_vhdl_testbench_generator.htm page.
Randomizes Data and Transaction Sequencing
The new version of TestBencher eliminates many of the manual coding steps that were previously required to create a testbench that applies a set of weighted-random transactions with contrained-random input data to a model under test. A fully randomized testbench with uniform transactor weightings can now be created without manually writing a single line of HDL code, although the tool supports a mixed-approach of manual and automatically-generated testbench code.
TestBench Generation Methodology
The user graphically draws timing diagrams that represent the protocols for the testbench's transactions with time and state variables to indicate transaction input data. A transactor is generated for each timing diagram and these transactors can be triggered by function calls made by the user in a testbench
