Test and Repair System is suitable for nanometer memories.
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Press Release Summary:
Enhancing manufacturing test quality for 45, 65, and 90 Nm memories, emBISTRx(TM) system features Advantage(TM) and Metro(TM) memory compilers, and embedded BIST/BISR controller. Minimizing area impact on memory sub-system through optimal partitioning of test and repair logic, system also reduces routing congestion and number of interconnects to enable faster testing. System has algorithms to detect memory faults such as excessive leakage, weak bits, and resistive shorts and opens.
Original Press Release:
ARM Introduces New Advanced Embedded Memory Test and Repair System for Nanometer Technologies
emBISTRx BIST/BISR Solution Optimizes Overall Memory Sub-System Area and Delivers Higher Chip Yield and Enhanced Test Quality
CAMBRIDGE, England, October 24 -- ARM [(LSE:ARM); (Nasdaq:ARMHY)] today announced the availability of its new advanced emBISTRx(TM) embedded memory test and repair system that is tightly integrated with the ARM® Advantage(TM) and Metro(TM) memory compilers, part of its family of Artisan® physical IP. The ARM fully embedded memory sub-system with integrated Built-in-Self-Test (BIST) and Built-in-Self Repair (BISR) IP increases overall chip yield to reduce chip cost, raise profit margins and enhance manufacturing test quality for Advantage and Metro memories for 45 nanometer (nm), 65 nm and 90 nm.
As memory content increases to thousands of individual memory instances in nanometer designs, system-on-chip (SoC) designers are challenged on multiple fronts, in managing the impact on design parameters such as power, performance and area. Additional areas of impact are development productivity, ensuring repairability for yield enhancement and high-test quality.
Unlike existing approaches where different controller types are required for different types of memory, the advanced ARM emBISTRx system is based on a hierarchically distributed architecture. With the ARM solution, a centralized shared BIST/BISR controller manages many different sizes and types of register files and memories with smart wrappers designed to be placed close to the memory instance. The benefit of ARM's integrated approach is that it minimizes the area impact on the overall memory sub-system through optimal partitioning of the test and repair logic between the controller, wrapper and memory macro. Depending on the design and implementation, average area reduction in the range of 20-30% can be observed as compared to conventional approaches.
Additionally, the ARM emBISTRx solution reduces the number of interconnects and routing congestion, which results in area savings and faster timing closure. This area efficient, architectural approach allows designers to optimize timing-critical paths and enables at-speed testing, a critical requirement for many high-speed consumer and enterprise applications.
To enhance design productivity, the ARM emBISTRx system includes an automation tool to insert and stitch the BIST/BISR logic into the design, which reduces implementation time and eliminates design errors. The ARM emBISTRx system is tightly integrated with the ARM memory compilers to offer designers an easy-to-use solution for implementing the ARM embedded memory sub-system.
In addition to the traditional approach of targeting standard memory fault types, the ARM emBISTRx system includes algorithms that detect real world silicon defects in nanometer technology such as excessive leakage, weak bits, and subtle behavior such as resistive shorts and opens that can result in low yield. The defect-based BIST algorithms are architected to minimize test escapes, which can potentially save millions of dollars in cost for high-volume products. The ARM emBISTRx system is tuned to ARM's specific memory redundancy architecture, which is based on memory defect data,
bit-cell yields and related foundry recommendations.
"As our customers move from 90nm to 45nm and beyond, they are facing many challenges to deliver higher yielding memories with robust test quality, and at the same time satisfy the area and timing constraints", said Neal Carney, vice president of marketing, Physical IP, ARM. "With the introduction of the ARM emBISTRx solution, we are delivering an area-optimized embedded memory sub-system tightly integrated with test and repair capability to enable our customers to meet their overall yield goals with high-test quality and higher profit margins. This solution simplifies the challenge of adding test and repair into complex SoCs enabling our customers to get to market quickly."
Availability
The ARM emBISTRx product will be available in Q4 2006 and pricing will be based on customers' selection of memories and process technologies.
About ARM
ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 16/32-bit RISC microprocessors, data engines, graphics processors, digital libraries, embedded memories, peripherals, software and development tools, as well as analog functions and high-speed connectivity products. Combined with the company's broad Partner community,
they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at www.arm.com
Source: ARM Ltd
Contact Details:
Michelle Spencer
ARM
+44-1628-427780
michelle.spencer@arm.com
Claudia Natalia
ARM
+1-408-548-3172
claudia.natalia@arm.com
