Press Release Summary:
Delivering OC-48 performance with sub 1 ps jitter output, single-chip Models ZL30116 and ZL30119 generate 3 independent clock families, eliminating need for external dividers or clock-multiplying PLLs. Devices deliver range of selectable output frequencies for low-jitter clocks, including 19.44, 38.88, 51.84, 77.76, 311.04, and 622.08 MHz. Providing holdover and hitless reference switching, chips ensure continued operation during network disruptions or upgrades.
Original Press Release:
Zarlink Simplifies Timing for SONET/SDH Networking Equipment with Industry's Lowest Jitter Single-Chip Synchronizers
- Synchronizers deliver OC-48 performance with sub-1 picosecond jitter output - Single device replaces three PLLs and multiple-clock distribution chips
OTTAWA, Dec. 15 / -- Zarlink Semiconductor (NYSE/TSX:ZL) today introduced the industry's first single-chip ultra-low jitter synchronizers for SONET/SDH multi-service applications. The feature- rich ZL(TM)30116 and ZL30119 PLLs (phase locked loops) are the lowest jitter and smallest devices for managing SONET/SDH Stratum 3 synchronization at OC- 48/STM-16 rates.
With the explosive growth of Ethernet and other packet-based traffic, carriers must protect their investments in SONET/SDH infrastructure while accommodating multiple traffic types. Network equipment vendors are developing SONET/SDH multi-service products, including MSPPs (multi-service provisioning platforms) and MSSPs (multi-service switching platforms) that allow carriers to mix voice and packet services by only replacing edge network elements. Industry research values this market at US$3.5 billion in 2005 with equipment installations predicted to grow 26% in 2006.
In turn, semiconductor companies are delivering next-generation ADMs (add- drop multiplexers), which are small, high-performance system-on-chip devices that process packetized traffic more efficiently. ADMs require multiple clocks to deal with multiple traffic types and only Zarlink's new timing chips offer ADM designers a comprehensive set of Stratum 3 clock synthesis capabilities while meeting OC-48/STM-16 performance requirements.
"Our new synchronization platform combines digital and analog PLL technology with advanced clock synthesis capabilities to give SONET/SDH multi- service equipment designers the performance they need," said Michael Rupert, product marketing manager, Zarlink Semiconductor. "The ZL30116 and ZL30119 chips offer maximum flexibility and ease of design while significantly reducing bill of material costs."
Leading network equipment vendors are currently evaluating Zarlink's new PLLs for their next-generation designs.
Full suite of output clocks and AdvancedTCA(TM) synchronization capabilities
The highly programmable ZL30116 and ZL30119 chips generate three independent clock families, eliminating the need for external dividers or clock-multiplying PLLs. The devices match the reference frequency requirements of any commercial SONET/SDH PHY (physical interface), and deliver the industry's widest range of selectable output frequencies for low-jitter clocks - 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHZ, 311.04 MHz and 622.08 MHz.
The ZL30116 device implements the market's most extensive suite of master/slave clock redundancy capabilities. This chip is the only synchronizer to embed zero delay PLL capabilities that compensate for external clock propagation delays to meet the stringent phase alignment requirements of AdvancedTCA clock busses.
Single-chip design saves space, manages jitter
Digital PLL-based synchronizers are used in SONET/SDH equipment to manage numerous clocks within a multi-service switching environment. However, most digital PLLs generate too much jitter for interfaces at rates above OC-3, necessitating a separate analog PLL to "clean up" the noise. Multi-chip combinations or modules may be as large as one square inch. Zarlink is first to deliver a single-chip synchronizer capable of generating less than 1 ps of jitter. The ZL30116 Stratum 3 system synchronizer and ZL30119 line card synchronizer are pin-compatible and measure just 9 x 9 mm.
Carrier-class network synchronization
The ZL30116 and ZL30119 devices provide superior network synchronization features including holdover and hitless reference switching. The chips ensure continued operation during network disruptions or upgrades by monitoring the input reference clocks and providing hitless reference switching upon detecting a bad or failed reference clock. The PLLs maintain stable and reliable output clocks in the presence of network or intra-system jitter and wander conditions.
If the source of network synchronization is temporarily lost, the devices automatically switch into holdover mode and continue to generate output clocks based on data collected from past reference signals.
The ZL30116 and ZL30119 PLLs are available now. For information, visit: products.zarlink.com/profiles/zl30116 or products.zarlink.com/profiles/zl30119. For more information on Zarlink's timing portfolio, visit: timing.zarlink.com/ .
About Zarlink Semiconductor
For over 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The Company's success is built on its technology strengths including voice and data networks, optoelectronics and ultra low- power communications. For more information, visit www.zarlink.com .
Shareholders and other individuals wishing to receive, free of charge, copies of the reports filed with the U.S. Securities and Exchange Commission and Regulatory Authorities, should visit the Company's web site at www.zarlink.com or contact investor relations.
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