Press Release Summary:
Accepting 10 CMOS clock reference inputs, Model STC5429 generates 10 synchronized clock outputs including 2 frame pulse clocks for frequencies ranging from 2 kHz to 156.25 MHz. Two independent timing generators, T0 and T4, may operate in Freerun, Synchronized, and Holdover modes. T0 supports master/slave and multiple master operation for redundant design, while T4 only supports master operation. Applications include Ethernet equipment clocks, DOCSIS, SDH/SETS, and SONET.
Original Press Release:
Connor-Winfield Announces New 9x9mm Hitless Switch Protection and Timing System for ITU-T-G.8262 EEC Options 1 and 2
Aurora, IL — The STC5429 is a single chip multi-service synchronization solution for applications in Ethernet Equipment Clocks, DOCSIS, SDH/SETS, and SONET. The QFN64 packaged device is fully compliant with ITU-T G.813 option 1 and 2, G.8262 EEC Opt1 and Opt2 and Telcordia GR1244 and GR253 standards.
The STC5429 accepts 10 CMOS clock reference inputs and generates 10 synchronized clock outputs including two frame pulse clocks for a wide variety of frequencies from 2kHz up to 156.25MHz. Reference inputs are individually monitored for activity and quality. Reference selection may be automatic, manual, and pin-selectable hard-wired modes.
Two independent timing generators, T0 and T4, may operate in the Freerun, Synchronized, and Holdover modes. Each timing generator includes a DSP-based PLL. Synchronized mode external timing while in freerun and holdover mode are self-timing. T0 supports Master/Slave and Multiple Master operation for redundant design. T4 only supports master operation. The DSP-based PLL technology requires only an external master reference oscillator at 10, 12.8 (default), 19.2 or 20 MHz. The SPI Bus interface reads and writes 117 registers for control and monitoring purposes. Programmable frequency synthesis, phase skew and bandwidth are some of the numerous functions.
• Complies with ITU-T G.813 Opt1/Opt2, G.8262 EEC Opt1/Opt2, Telcordia GR1244 and GR253 (Stratum3/4E/4/SMC)
• Two timing generators T0 and T4; T4 may lock to T0’s synchronized output
• Supports Master/Slave and Multiple-Master redundant application (T0 timing generator only)
• Provides programmable compensation for phase delay between master and slave unit, in 0.1ns steps
• Accepts external oscillator at frequency of 10MHz, 12.8MHz, 19.2MHz,or 20MHz with programming
• Accepts 10 clock reference inputs
• Supports frequency auto detection or manually acceptable frequency for reference inputs. Each of them is monitored for activity and quality
• Automatic/manual/hard-wired manual reference select
• Outputs 10 synchronized clock outputs, including 2 frame pulse clocks CLK8K and CLK2K
• 10 clock synthesizers generate frequencies
• Programmable phase skew in synthesizer level
• Phase-align or hit-less reference locking/switching
• Programmable loop bandwidth, from 0.1Hz to 100Hz
• Supports SPI bus interface
• Single 3.3V operation
• IEEE 1149.1 JTAG boundary scan
• Available in ROHS Compliant QFN64 package
Pricing: $12.00 at 1K
For more information contact:
The Connor-Winfield Corporation; Tel: 630.851.4722; www.conwin.com; firstname.lastname@example.org