Structured ASIC Solution has fine-grained architecture.
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Manufactured on TSMC's 90 nm process, HardCopy® II devices feature FPGA front-end design methodology. Interface circuitry supports external memory at 233 MHz for SDRAM and 250 MHz for RLDRAM II. Devices deliver up to 2.2 million ASIC gates, 8.8 million bits of RAM, and over 350 MHz system performance. They support 1 Gbps differential I/O as well as high-speed interfaces such as 10-Gigabit Ethernet (XSBI), HyperTransport(TM), SFI-4, and RapidIO(TM).
Original Press Release:
Altera Unveils HardCopy II: Industry's Most Compelling Structured ASIC Solution
San Jose, Calif., January 24, 2005-Altera Corporation (NASDAQ: ALTR) today announced the HardCopy® II family, its next-generation structured ASIC solution. HardCopy II devices are the industry's most compelling structured ASICs, featuring a unique FPGA front-end design methodology and costs as low as $15 for 1 million ASIC gates. Built on a new fine-grained architecture designed for low cost, HardCopy II structured ASICs deliver a level of gate densities, performance, and low power consumption that make them the best solution for a broad range of ASIC and ASSP implementations.
HardCopy II devices deliver up to 2.2 million ASIC gates, 8.8 million bits of RAM, and over 350-MHz system performance. The HardCopy II family's cost, density and performance will extend Altera's reach into the wireline and wireless communication, storage, digital consumer, industrial, and military markets, where Altera's structured ASIC solutions are already being successfully adopted.
Huawei's director of fixed network hardware Jing Yangbao comments, "HardCopy structured ASICs have several advantages compared with standard ASICs. The first is lower total cost, the second is shorter development time and faster time-to-market, and the third is the seamless migration from an FPGA to a HardCopy device. With these advantages, we have more options to increase the success of our products."
"Altera's HardCopy structured ASIC gave us the flexibility of an FPGA and the performance of a standard-cell ASIC, uniquely meeting our combined cost, performance, and time-to-market goals," said Richard Jaenicke, director of product management at Mercury Computer Systems, Inc. "The fabrication of the HardCopy devices went very smoothly, and the devices were better than advertised-it took us only half a day to verify their functionality and performance. Based on our experience of using HardCopy devices, we would definitely use them again for a similar project."
"Why Choose Anything Else?"
Altera offers the only structured ASIC development process with seamless migration from a pin-compatible, functionally equivalent FPGA prototype. This process minimizes development risk and development cost compared to any other ASIC or structured ASIC solution. Using the Quartus® II design software and the Stratix® II FPGA family, designers can fully validate their design in system and at speed. They can also test-market features, and even develop multiple variations of a design, before committing to silicon. Once engineers finalize their design, the Quartus II design software automatically generates the files to hand off to Altera's HardCopy Design Center. The HardCopy Design Center performs a turnkey migration of the design to a HardCopy II structured ASIC and delivers fully tested prototypes in 8 to 10 weeks.
Collett Research International estimates that more than 60 percent of ASIC designs need to be re-spun at least once, leading to product delays and cost overruns. The Altera structured ASIC design methodology helps designers avoid costly re-spins and lowers the total cost of ownership by dramatically shortening the time it takes to bring a product to market. With version 4.2 of Altera's Quartus II design software, released in December, designers can prototype their HardCopy II design and lay out their printed circuit board immediately, knowing that Altera's unique seamless migration process will ensure that they will get a true drop-in replacement of their FPGA when they move into production.
"Why choose anything else?" said Alain Bismuth, Altera's vice president of the HardCopy product group. "The new price, performance, density, and power features of HardCopy II structured ASICs combined with the FPGA front-end for design verification offers ASIC designers the most efficient methodology for system-level design. Additionally, the enormous time-to-market benefit customers derive from Altera's structured ASIC offering is unequaled by any other structured ASIC or standard-cell ASIC solution on the market."
Designers have the option to use their existing synthesis, verification, timing analysis, and logic equivalency checking tools from Cadence, Mentor Graphics, Synopsys, and Synplicity. ASIC and FPGA designers can target HardCopy structured ASICs with their existing design flows, minimizing the need for any additional tools training or increased development costs.
HardCopy II Features
HardCopy II devices deliver over 50 percent core power reduction from the design implemented in the Stratix II FPGA. Its interface circuitry supports external memory at 233 MHz for SDRAM and 250 MHz for RLDRAM II. Additionally, HardCopy II devices also support 1-Gbps differential I/O and high-speed interfaces, including 10-Gigabit Ethernet (XSBI), SFI-4, SPI 4.2, HyperTransport(TM), RapidIO(TM), and UTOPIA Level 4 interfaces up to 1 Gbps.
As with the previous HardCopy families, HardCopy II devices are built on the same process as the FPGA used as prototypes, enabling a seamless, risk-free design migration and delivering a drop-in replacement of the FPGA. HardCopy II devices are manufactured on TSMC's 90-nm process with low-k dielectric, the same process as the Stratix II FPGA family.
Pricing and Availability
Designers can immediately begin prototyping their HardCopy II designs on a Stratix II FPGA using Quartus II version 4.2 design software. Customer prototypes of the first HardCopy II device will be available in the third quarter of 2005. The HardCopy II family has five members ranging in density between 1 million and 2.2 million ASIC gates. Volume pricing at 100,000 units starts at $15, with NREs starting at $225,000 for a full turnkey migration, including delivery of fully tested prototypes. Find out more about Altera's HardCopy II structured ASICs at www.altera.com/hardcopy2.
About Altera
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com
Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder. HyperTransport is a trademark of the HyperTransport Consortium, and RapidIO is a trademark of the RapidIO Trade Association.
