Stripping System cleans low-k materials without damage.
Press Release Summary:
ES3LK 300 mm photoresist plasma stripping system provides zero-damage process for low-k materials, capping layers and etch stops used in low-k integration schemes through 45 nm technology node. Stand-alone, isotropic, dry-strip system maintains lowest k-effective value for integrated back-end-of-line dielectric stacks. It is compatible with subsequent wet cleaning steps and can be used with virtually all dense and porous low-k materials.
Original Press Release:
Axcelis Introduces Photoresist Dry Strip System for Low-k Dielectrics
New ES3Lk provides unique process capability for damage-free cleaning of low-k materials
BEVERLY, Mass. - May 27, 2003 -Axcelis Technologies, Inc. (NASDAQ: ACLS) today introduced the ES3Lk, a novel 300mm resist stripping system specifically designed to support the integration of low-k dielectric materials. The ES3Lk is the industry's first plasma stripping system to provide a zero-damage process for low-k materials, capping layers and etch stops used in low-k integration schemes through the 45nm technology node. A stand-alone dry strip system, the ES3Lk gives chipmakers up to 25% lower cost of ownership than in situ etch/strip tools, where the etch and strip process are performed in a single process chamber.
Photoresist removal processes represent one of the top five challenges to low-k integration, according to the International Technology Roadmap for Semiconductors. This is because conventional dry cleaning processes introduce latent damage in low-k materials, leading to adverse changes in the dielectric and the material's physical properties; these changes are especially evident after a wet cleaning step.
"Low-k dielectrics can only improve device performance if chipmakers have the tools and processes that enable them to overcome the unprecedented integration challenges associated with these sensitive materials," said Jan-Paul van Maaren, vice president and general manager of Axcelis Curing and Cleaning Systems. "By working closely with our customers, industry research laboratories and low-k materials suppliers, Axcelis has been able to deploy non-damaging chemistries on a robust dry strip platform. The result is a new process that preserves the insulating and structural properties of the low-k materials that chipmakers are adopting for dual-damascene chip designs, both today and for years to come."
The result of several years of focused R&D activity and extensive field verification, the Axcelis ES3Lk is a new isotropic dry strip system that maintains the lowest k-effective value for integrated back-end-of-line (BEOL) dielectric stacks. Compatible with subsequent wet cleaning steps, the ES3Lk process can be used with virtually all dense and porous low-k materials, allowing customers to extend the process across several technology generations.
Based on Axcelis' FusionES3 platform, which has been adopted by chipmakers worldwide for its reliability, productivity and process performance, the ES3Lk gives chipmakers the ability to meet high-volume production goals. The tool is a stand-alone dry strip system, which offers up to 25 percent lower cost of ownership compared to integrated in situ etch/strip systems. The system's unique downstream microwave chamber design provides consistent strip rates, high process uniformity and excellent selectivity to low-k materials, while integrated load lock chambers ensure process integrity.
Presentation and Reception at IITC
Axcelis technologists will be available to discuss the ES3LK technology during IEEE's International Interconnect Technology Conference (IITC) being held June 2-4, 2003, in Burlingame, Calif. Customers and press are invited to visit the Axcelis booth, #212, during the two-day conference. In addition, Axcelis will present co-authored papers on the ES3Lk technology during its IITC process seminar on June 2. Press interested in attending the reception should contact Stacy Grisinger at Loomis Group, +1 (617) 638-0022 or grisingers@loomisgroup.com.
About Axcelis Technologies, Inc.
Axcelis Technologies, Inc., headquartered in Beverly, Massachusetts, provides innovative, high-productivity solutions for the semiconductor industry. Axcelis is dedicated to developing enabling process applications through the design, manufacture and complete life cycle support of ion implantation, rapid thermal processing, and cleaning and curing systems. Axcelis Technologies has key technology centers in Beverly, Massachusetts, and Rockville, Maryland as well as in Toyo, Japan through its joint venture, SEN. The company's Internet address is: www.axcelis.com.
