Software supports flash-based FPGA devices.
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Press Release Summary:
Libero 6.1 Integrated Design Environment is optimized for flash-based ProASIC3 and ProASIC3E devices, and delivers efficient and seamless flow through simulation, synthesis, and place-and-route. Technology enables designers take advantage of on-chip FlashROM function, which can be programmed independent of the FPGA core. Applications include device serialization, Internet protocol addressing, and version control.
Original Press Release:
Actel's Libero Integrated Design Environment Delivers Optimized Support for New ProASIC3 and ProASIC3E Flash-Based FPGA Families
Software Allows Customers to Fully Leverage All Architectural Features and Performance of the New Low-Cost Devices and Enables Device Serialization
MOUNTAIN VIEW, Calif., Jan. 24 -- In conjunction with its introduction of the industry's lowest cost field-programmable gate arrays (FPGAs), Actel Corporation (NASDAQ:ACTL) announced that its Libero 6.1 Integrated Design Environment (IDE) provides complete support for the company's new flash-based ProASIC3 and ProASIC3E devices (See separate press release entitled, "Actel's Third-Generation Flash-Based Devices Set the Bar at $1.50 as Industry's Lowest Cost FPGA Solution"). The Libero 6.1 IDE contains a range of performance, resource optimization and ease-of-use features that, combined with leading third-party design tools, deliver an efficient, seamless flow through simulation, synthesis and place-and-route. The software is optimized to exploit the architectural features of the ProASIC3 and ProASIC3E devices, including the unique on-chip FlashROM (FROM), which can easily be programmed independent of the FPGA core.
"As the industry's first FPGAs with on-chip FlashROM and a host of advanced features, the ProASIC3/E devices offer designers an unprecedented level of functionality at an extremely low price point," said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel. "We have extensively tested this enhanced tool suite over several months to ensure that Libero IDE 6.1 addresses and exploits all of the silicon features in a robust and intuitive design environment. In turn, our customers can achieve optimized performance for these next-generation devices with complete confidence."
Simple Flow Enables the Industry's First FPGA FlashROM Implementation
The Libero IDE applies innovative new technology to help designers take advantage of the FROM function of the ProASIC3/E devices, which can be easily programmed independent of the FPGA core for applications, such as device serialization, Internet Protocol (IP) addressing and version control. A new FlashPoint Programming File Generator integrates preset FROM macros, including device serialization, allowing customers to merge the FPGA configurations and the FROM programming file. The FlashPoint Programming File Generator also enables all encryption capabilities for the FROM contents, such as security header, encryption key and FlashLOCK security. Using the FlashPoint software, designers can change the functionality of the FROM after the completion of the ProASIC3/E design process while preserving the security of the ProASIC3/E core logic.
Actel's ACTgen core builder now provides a comprehensive user interface to ensure simple implementation and seamless flow of various FROM content options into the hardware description language (HDL). Custom FROM applications can be input via a data table or read as a text file. Users can also specify a built-in feature that provides auto increment or decrement during the programming process. This enables each device to have a unique serial number for specialized applications.
Leading-Edge Phase Lock Loop (PLL) Configuration
The ACTgen core builder has a new "Visual PLL" interface that provides a wide range of PLL programming options to dramatically ease the setting of accurate PLL parameters. Using customizable clock conditioning circuitry in the PA3/E devices, the designer can adjust frequency and feedback settings, and set various detailed parameters for clock applications via "tailor-made" PLL schematics.
Optimizing PA3/E Features
The Libero 6.1 IDE includes a MultiView Navigator I/O Attribute Editor that enables easy selection and programming of up to 19 I/O standards within ProASIC3/E devices, thereby streamlining the physical implementation process.
The tool suite offers complete support for the high-speed ProASIC3/E VersaNet Global Network to allow mapping for up to 252 different internal or external clocks within the ProASIC3/E FPGAs. The ChipPlanner, Physical Design Constraints (PDC) and Magma PALACE (Physical and Logical Automatic Compilation Engine) physical synthesis tools provide full support of VersaNet Global Networks, thus simplifying the use of all physical constraint flows. Libero 6.1 Timing Driven Place and Route, coupled with Synplicity's Synplify and Magma's PALACE tools, ensure PA3/E product performance of 66 MHz 64-bit PCI performance -- the highest level of performance for any value-based FPGA.
Pricing and Availability
The Actel Libero 6.1 IDE is available in three editions: Platinum, Gold and Silver. The Platinum version sells for $2,495, the Gold version sells for $595 and Silver is a free version. All are one-year renewable licenses. For further information about pricing and availability, please contact Actel.
About the Libero Integrated Design Environment
Actel's Libero 6.1 IDE offers best-in-class tools from EDA leaders, such as Magma, Mentor Graphics, SynaptiCAD and Synplicity, and custom-developed tools from Actel integrated into a single FPGA development package. The Libero tool suite supports mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules within a design.
About Actel
Actel Corporation is a supplier of innovative programmable logic solutions, including field-programmable gate arrays (FPGAs) based on antifuse and flash technologies, high-performance intellectual property (IP) cores, software development tools and design services targeted for the high-speed communications, application-specific integrated circuit (ASIC) replacement and radiation-tolerant markets. Founded in 1985, Actel employs more than 500 people worldwide. The Company is traded on the Nasdaq National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, CA, 94043-4655. Telephone: 888-99-ACTEL (992-2835). Internet: www.actel.com/.
