Software provides pre-silicon system validation.
Press Release Summary:
SPEEDCompiler(TM) and DesignPlayer(TM) enable thousands of users to simultaneously develop and test software on RTL hardware implementation model. SPEEDCompiler reads Verilog RTL and generates linkable object representation that is cycle and register accurate. It includes C API for system integration and interrogation manager for design debug. DesignPlayer engine incorporates SPEEDCompiler object to create deployable runtime model of chip or IP block.
Original Press Release:
Carbon Design Systems Announces Product Offering, Rolls High-Performance, Pre-Silicon Validation Suite
WALTHAM, MA, December 1, 2003, Carbon Design Systems, a new EDA company announced today the general availability of its SPEEDCompiler(TM) and DesignPlayer(TM) suite of tools that enables pre-silicon system validation, where thousands of users can simultaneously develop and test software on the 'golden' RTL hardware implementation model.
System validation is accomplished today with large amounts of labor and material expenditures including tailor-made software models, silicon prototypes, and FPGA breadboards. The lack of fast, accurate, soft-models of chips and systems that can be economically deployed has largely kept system validation in the critical path to product release and profit.
Carbon's tool suite moves validation ahead of silicon fabrication. This shaves months off time-to-profit by allowing concurrent validation of software and hardware, enabling system integration to begin months earlier, and collapsing customer-win cycles.
Carbon's SPEEDCompiler software reads industry standard Verilog RTL and generates an ultra-high performance linkable object representation that is both cycle and register accurate. In addition, this object includes a 'C' API for system integration and an interrogation manager for design debug. Carbon's SPEEDCompiler patent-pending technology creates objects that will execute at thousands of cycles per second, on millions of gates, while remaining bug-for-bug accurate with the target hardware.
Carbon's DesignPlayer engine incorporates a SPEEDCompiler object to create a deployable runtime model of a chip or IP (intellectual property) block. At the system level, DesignPlayer engines can represent multiple chips that encompass hundreds of millions of gates. DesignPlayer engines by their nature are secure-the RTL can't be recovered-solving another IP deployment issue.
In practice, software engineers validating their critical foundation software-drivers, diagnostics, and firmware-on Carbon's DesignPlayer engine, may uncover hardware bugs, as well as, software bugs. The built-in interrogation manager enables the root cause to be quickly traced with complete control and visibility of signals and memories. After the RTL is fixed, a simple compile with Carbon's SPEEDCompiler software delivers a DesignPlayer engine ready for validation.
There are a multitude of existing solutions attempting to address system validation with limited customer traction. Hardware-based validation runs fast, but isn't deployable on a broad scale for obvious cost and update barriers. This quickly eliminates emulators, hardware-assisted simulation accelerators, and FPGA breadboards. Hand-crafted custom 'C' models and behavioral models are software-based, but not generated from the 'golden' RTL. Validating software on simulators is orders of magnitude too slow. Only Carbon's DesignPlayer engine has the speed, accuracy, and software deployment to enable system validation for the masses.
"We wanted to employ RTL hardware models for software driver validation, but hit a simulation wall of 8 days per iteration," declared Carey McMaster, director of software engineering at StarGen. "DesignPlayer reduced our validation turn-time from 8 days to 8 minutes and performed distributed discovery on a 20 node switch fabric that encompassed over 15 million gates."
"Software development on the hardware implementation model is the key to a successful validation strategy," said Steve Butler, president and chief executive officer at Carbon. "This eliminates the risk and re-verification associated with custom models, model accuracy, and the massive cost of developing and maintaining multiple models for hardware and software evelopment. With DesignPlayer, one common model is used across the system development lifecycle. This common model is RTL, the industry standard for driving the backend layout tools for fabrication."
Pricing and Availability
Carbon's DesignPlayer and SPEEDCompiler software products are shipping now with pricing based on an annual subscription volume model. SPEEDCompiler software is priced at $150,000 per seat and DesignPlayer engines are under $10,000 per seat for high volume purchases.
About Carbon
Carbon is delivering software products that enable pre-silicon system validation, where thousands of users can simultaneously develop and test software on the 'golden' RTL hardware implementation model. For the first time, critical foundation software-drivers, diagnostics, and firmware-runs at KHz execution speed on the 'golden' model with cycle and register accuracy. This opens the door for system validation and IP deployment to begin much earlier than traditional methods.
Carbon Design Systems, Inc. is privately held and funded by Flagship Ventures and Commonwealth Capital. The corporate headquarters is located at 375 Totten Pond Road, Suite 200, Waltham, MA. 02451. Telephone: 781.890.1500, Facsimile: 781.890.1711, Email: info@carbondesignsystems.com, Website: www.carbondesignsystems.com or SPEEDCompiler.com
Carbon Design Systems, SPEEDCompiler, and DesignPlayer are trademarks of Carbon Design Systems, Incorporated. All other companies and products referenced herein are trademarks or registered trademarks of their respective holders.
