Software facilitates ASIC design flows.
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Press Release Summary:
Library Smart(TM) enables design optimization using multiple libraries on same die with simultaneous analysis of multiple process, temperature, and voltage corners. Technology centralizes, organizes, and manages library data to optimize ASIC design flows. It enables EDA tool developers to create tools that bridge disconnect between semiconductor IP and EDA tools. Software automatically analyzes Design Kits and provides results for template customization.
Original Press Release:
Silicon Navigator Unveils Library Smart Technology(TM) - Multi-dimensional Optimization Enabler
Software closes gap between EDA tool and library Design-Kit providers, Technology enables multiple libraries to be on the same die & simultaneous analysis of multiple PVT corner cases
Cupertino, Calif. -- June 1, 2005-- Silicon Navigator Corporation launches new Library Smart(TM) technology that revolutionizes EDA tool intelligence for its Rocket Framework (introduced in April). Library Smart technology enables a new class of design optimization using multiple libraries on the same die with simultaneous analysis of multiple PVT (Process, Temperature and Voltage) corners.
Library Smart technology centralizes, organizes and manages library data with best-practices to make ASIC design flows simpler. It gives EDA tool developers a head start on creating tools that bridge the growing disconnect between Semiconductor IP (Design Kits for a specific process node) and EDA tools.
"We developed Library Smart technology to enable the capture of design implementation intent in Design Kits. We see this as a key differentiator in our Rocket Framework and optimization flows," said Silicon Navigator CEO J. George Janac. "We realize that the reference library dictates many of the best practices used in chip implementation.
Silicon Navigator closes the gap between the tacit knowledge that is embedded in today's Semiconductor IP but lost to EDA tools. Today there is no substitute for the tall-thin designer that understands all facets of both reference libraries and chip design. A high degree of design intent is often lost between Semiconductor IP designers and chip designers. The critical information required for project success is usually referenced in obscure application notes and rarely captured by EDA tools. Up to now, it has been up to the chip architects and Silicon IP experts to sort out the critical knowledge embedded in the 2 - 4 giga bytes of Design-Kit data.
Optimization Capabilities
Library Smart is organized on the principles of design once and measure many times. Chip timing, power and packaging must be designed to work under worst case conditions. However, electronic consumer products involve an ever increasing range of power profile modes, nominal temperatures and operating conditions dictated by the product environment. Optimization must operate under a range of user selectable operating points, not just at the worst case corners.
"EDA tools must understand the limits of libraries for timing, power and leakage. Otherwise, designers are forced to run endless iterations in disparate timing, and power tools," said Steve Potter VP of Engineering. "Optimization tools do what they are told but with Library Smart technology they can make more effective decisions on efficiency and cost of implementation."
Verification model complexity is growing exponentially because of DFM-related issues. Optimization models must be both high level, enabling quick turnaround time, and physically accurate to assure convergence. Multiple levels of model abstraction are a core benefit for Library Smart tools.
Design-Kit Organization
Design-Kit data (as provided by Semiconductor IP vendors) is organized via indices to LEF, Liberty, Milkyway and binary tool formats without re-organization. C++ API's enable quick tool integration and customization. Macro-modeling and analysis is performed in order to extract library behavior, operational limits and establish best practices.
"Perhaps the main reason that FPGA design flows are simpler is that these tools are bundled with their best practices and Design-Kit data," said Janac. "We want to build Library Smart technology into the same paradigm, bringing greater simplicity to ASIC and COT flows."
Vendors and users can embed their own best practices in Library Smart. Power Grid construction, I/O Frame electrical assembly, gated clocks, etc. can all be captured for implementation tools. Silicon Navigator's tools automatically analyze given Design Kits and provide analysis results for template customization.
Pricing and Availability
Library Smart data organization is provided in Silicon Navigator's Rocket Framework products. Library Smart software comes bundled with a C++ programming API form for direct incorporation into in-house applications. Pricing starts at $50K for development seats. Silicon Navigator will be demonstrating Library Smart technology and optimization tools at the Design Automation Conference (www.dac.com) in Anaheim, CA, at booth 2241, the week of June 13.
About Silicon Navigator
Silicon Navigator is a private company dedicated to modular EDA software development. The company provides software components and engines accessible at the C++/Tcl levels for use as building blocks for in-house tool development and as a platform for emerging EDA companies' tool development. The company offers EDA applications and software components based on the Si2 OpenAccess database standard. It is the only startup on the OpenAccess Change Control Team representing the interests of EDA startups and customers needing modular EDA solutions.
Silicon Navigator corporate headquarters are located at: 10050 North Wolfe Road, Suite SW2-260, Cupertino, Calif. 95014. Telephone: 408-200-0280. Facsimile: 408-200-0281. Email: info@SiNavigator.com. Website: www.SiNavigator.com.
Library Smart and Silicon Navigator are trademarks of Silicon Navigator. Silicon Navigator acknowledges the trademarks or registered trademarks of other organizations for their respective products and services.
