Software accelerates C language subroutines into hardware.

Press Release Summary:

Nios® II C-to-Hardware Acceleration (C2H) Compiler provides developers of embedded systems with tools needed for productivity. It automatically converts performance-critical C language subroutines into hardware accelerators and integrates them into FPGA-based Nios II subsystems, reducing development time to minutes. Software provides third-party tool vendors with access to system-level infrastructure, including Quartus® II SOPC Builder tool.

Original Press Release:

Altera Announces New Tool for Easily Accelerating C Into Hardware for Nios II Processor-Based Systems

Altera Also Provides Third-Party Access to Underlying System-Level Infrastructure

Embedded Systems Conference, San Jose, Calif., April 3, 2006-Altera Corporation (NASDAQ: ALTR) today announced the Nios® II C-to-Hardware Acceleration (C2H) Compiler, a new productivity tool for developers of Nios II-based systems that substantially increases the performance of their embedded software. As the number of embedded designs using FPGAs increases, the availability of the Nios II C2H Compiler is targeted at providing developers of embedded systems with the tools they need to be productive and successful. As part of the Nios II C2H Compiler offering, Altera is also providing third-party tools vendors with access to its system-level infrastructure, including the Quartus® II SOPC Builder tool, to foster development of a wide range of Electronic System Level (ESL) design tools.

The Nios II C2H Compiler leverages Altera's system-level infrastructure to deliver substantial performance improvement across a broad range of applications. The new tool automatically converts performance-critical C language subroutines into hardware accelerators and integrates them into FPGA-based Nios II subsystems, reducing development time from weeks to minutes. Attendees to the Embedded Systems Conference can see a demonstration of the Nios II C2H Compiler at Altera's booth (#1238) during exhibition hours.

Jordan Plofsky, Altera's senior vice president of marketing, explains: "Since Altera introduced its Nios soft processor core in 2000, many users have added hardware accelerators and custom instructions to improve system performance by eliminating repeated strings of sequential processor code. However, designing hardware accelerators and integrating them into the processor subsystem is a laborious manual task." Plofsky continues, "The Nios II C2H Complier automates these tasks to provide our large base of Nios II users improved productivity and performance. In addition, by providing access to our underlining system-level infrastructure to our partners, we are taking a crucial step in providing our customers with a wider range of choices for implementing their embedded designs with FPGAs."

Leveraging the Power of SOPC Builder
The Altera® Nios II C2H Compiler supports standard ANSI C code and delivers effective and efficient acceleration results across a wide range of application code, including operations accessing local and external memory and peripherals. It successfully tackles external memory operations, such as pointer dereferencing and array accesses, by leveraging the high-bandwidth Avalon® interconnect fabric generated by the Quartus II SOPC Builder tool. The Nios II C2H Compiler analyzes the memory interface profile of the code targeted for acceleration, and creates both hardware accelerator logic and the appropriate Avalon master and slave interfaces that match the memory latency. In this way, both the data computation and the memory access are offloaded from the Nios II processor, freeing it for other tasks. Because the Avalon interconnect fabric does not limit the number of masters and slaves, the Nios II C2H Compiler is able to produce as many memory-autonomous hardware accelerators as necessary to convert the target code.

The Nios II C2H Compiler enables Nios II users to improve system performance with minimal increases in resource utilization. In fact, the Nios II C2H Compiler delivers performance between 10 and 45 times greater than nonaccelerated software, yet only requires additional logic of 0.7 to 2.0 times the size of the processor alone, across a set of software applications including autocorrelation, bit allocation, convolution encoder, color space conversion and fast Fourier transform (FFT).

The Nios II C2H Compiler is a plug-in to the Eclipse-based Nios II integrated development environment (IDE), giving Nios II software developers a consistent and familiar interface. All hardware-accelerator generation tasks performed by the Nios II C2H Compiler are invoked and run from within the Nios II IDE, ensuring that users have a single tool interface for the entire acceleration flow. After profiling their application, users right-click to accelerate time-critical functions using the Nios II C2H Compiler, generating hardware accelerators that automatically link into the software flow.

Opening Technical Access to Altera's System-Level Infrastructure
To enrich Altera's ongoing work with its partners to create a broad set of ESL tools and interoperable methodologies, Altera has opened up application programming interfaces (APIs) to both its SOPC Builder system-level development tool and the Nios II IDE. This allows partners to develop tools more quickly by leveraging Altera's investments in system infrastructure that underpin the new Nios II C2H Compiler, such as memory latency awareness and master-slave interface inference.

"Designers already use our DK Design Suite and programmable logic devices to quickly create very high-performance, low-power algorithm accelerators or coprocessors," said Phil Bishop, CEO of Celoxica. "Customer feedback signaled the importance of Altera's SOPC Builder tool and the Avalon interconnect fabric, and as a result, DK can automatically generate SOPC Builder components from the software algorithms identified for acceleration. Opening up APIs for SOPC Builder and the Nios II IDE will stimulate further collaboration and meet the growing demands for efficient processor off-load to FPGAs."

Pricing and Availability
The Nios II C2H Compiler is currently shipping to beta customers and will be available for general release in May 2006. It will be delivered as an integrated plug-in to the Nios II IDE, and will be licensed separately for $2,995 per seat.

About Nios II Embedded Processors
The Nios II soft embedded processor is a general-purpose 32-bit RISC CPU optimized for programmable logic and system-on-a-programmable-chip (SOPC) integration. With over 15,000 development kits sold worldwide and the world's top 20 OEMs already using the Nios II processor, the Nios architecture is the most popular configurable soft processor available today. For more information, visit Developers can also visit the Nios Forum, an independent user group for Nios-based systems at For more information about the Nios II C2H Compiler, please visit

About Altera
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in SOPC solutions. Combining programmable logic technology with software tools, intellectual property and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder.

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