Simulation Software includes multithreaded HDL compilation.
Press Release Summary:
Active-HDL v7.3 is mixed-language design creation, FPGA project management, and simulation environment supporting VHDL, Verilog, SystemVerilog, and SystemC. It includes Accelerated Waveform Viewer that enables opening, zooming, scrolling, viewing, and management of 4 GB and larger files. Supporting VHDL 2002 and 2006 constructs, it features VHDL compiler that supports source files containing protected envelopes, file types, and aliases inside VHDL 2002 protected types.
Original Press Release:
Aldec Releases Active-HDL 7.3 and Introduces Multi-Threaded HDL Compilation
Henderson, Nevada - December 20, 2007 -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced today the release of Active-HDL 7.3. The release includes multi-threaded HDL compilation, new waveform viewer and expanded VHDL 2006 construct support. A noticeable performance improvement in VHDL, Verilog and mixed RTL compilation and simulation is included as part of the release. Active-HDL is a mixed-language design creation, FPGA Project Management and simulation environment supporting VHDL, Verilog, SystemVerilog, and SystemC.
Multi-threaded VHDL Compilation
Aldec has implemented multi-threaded compilation for VHDL designs. If Active-HDL 7.3 is installed on machines with multi-core CPUs, the compilation process can be up to 3 times faster. The compilation time of source files based on single processor has been reduced by 40% on average in comparison to the previous version of Active-HDL.
New Advanced Waveform Viewer
In addition to the Standard Waveform Viewer/Editor, Active-HDL 7.3 now offers the full integration of a new and high-performance Accelerated Waveform Viewer. The new high performance waveform viewer is backward compatible and enables opening, zooming, scrolling, viewing and management of large files (4GB and larger) almost instantaneously. Active-HDL 7.3 can read and write from the waveform database up to 4x faster then previous releases, while decreasing system memory requirements and file size.
Signals, including Verilog memories or large VHDL records can be expanded without delay. The new waveform viewer is optimized to support all design sizes and long simulation runs making it ideal for designers utilizing the largest devices from Altera Stratix® III and Xilinx Virtex(TM) 5.
VHDL 2002 and 2006 Support
Active-HDL 7.3 includes enhanced support for VHDL 2002 and 2006 constructs and now supports protected types introduced in the 2002 revision of the VHDL standard (IEEE Std 1076-2002(TM)). The VHDL compiler can now compile source files containing protected envelopes, file types and aliases inside VHDL 2002 protected types.
Availability
Active-HDL is available in four Product Configurations - Desktop Master (DM), Designer Edition (DE), Plus Edition (PE) and Expert Edition (EE). The software is available in floating or node-locked configurations.
Active-HDL 7.3, is available today and is sold directly from Aldec and its authorized world-wide distributors. Download a FREE evaluation copy of Active-HDL 7.3 today.
About Aldec
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. The company strongly believes that to be productive in today's market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers' designs. Additional information about Aldec is available at www.aldec.com.
Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Contact:
Dave Rinehart
Aldec, Inc.
(702) 990-4400 ext. 205
dave@aldec.com
