Physical Layer Device suits 10GBASE-LRM applications.
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Press Release Summary:
Providing full implementation of IEEE 802.3ae 10 Gigabit Ethernet PHY layer functionality, Puma AEL1003 includes electronic dispersion compensation features to meet IEEE 802.3aq specification for 10GBASE-LRM. It has 4-lane 3.125 Gbps XAUI system-side interface, with 10G serial line-side interface appropriate for implementation within XENPAK/XPAK/X2 MSA-based optical modules. Device includes PRBS and packet-level test pattern generators and checkers for BIST functions.
Original Press Release:
Aeluros Announces Industry's First Integrated EDC/10G PHY for 10GBASE-LRM Applications
Aeluros to Demonstrate Integrated EDC/10G PHY at OFC/NFOEC in Anaheim, CA (7-9th March, 2006)
MOUNTAIN VIEW, Calif., March 1 / -- Aeluros, the leading supplier of low-power CMOS based 10G PHY solutions, today announced its next generation 10GbE PHY/SerDes devices with integrated electronic dispersion compensation (EDC) capability. The Puma AEL1003 device provides full PCS, PMA, and XGXS sub-layer functionality, retains the unique cost savings features of the previous generation of 10G PHY devices, and adds EDC functionality for 10GBASE-LRM compliance. Aeluros will demonstrate the device at the upcoming OFC/NFOEC trade show in Anaheim, CA from 7-9 March, 2006 (Booth #3283).
The Puma AEL1003 device provides a full implementation of the IEEE 802.3ae 10 Gigabit Ethernet PHY layer functionality, along with the electronic dispersion compensation features to meet the IEEE 802.3aq specification for 10GBASE-LRM. The device also has a 4-lane 3.125 Gbps XAUI system-side interface, with a 10G serial line-side interface appropriate for implementation within XENPAK/XPAK/X2 MSA-based optical modules. The Puma AEL1003 device is XENPAK register-set compliant, supports the use of external DOM devices or microcontrollers and includes integrated PRBS and packet-level test pattern generators and checkers for effective device and module built-in self test (BIST) functions. Aeluros has also included a clock synthesizer into the AEL1003 that allows for operation with an inexpensive 50MHz source. This feature, along with BIST functions for modules and small packaging, allows modules manufacturers to effectively lower costs by simplifying module design and testing.
"The LRM market is expected to show robust growth in the next 2 years, becoming a significant market segment by 2008. Fueling this growth will be integrated PHY/EDC devices like the AEL1003 from Aeluros," said Jag Bolaria, Senior Analyst at The Linley Group. "Aeluros has continued its track record of delivering industry leading performance and integrated functionality with the Puma AEL1003 -- the latest member of its 10G PHY portfolio."
"We look forward to demonstrating the first integrated 10G PHY/EDC device at OFC," said Don Stark, Vice President of Engineering at Aeluros. "This integration, together with the device's onboard clock synthesizer and small inexpensive package, enables introduction of low cost 10GBASE-LRM optical modules."
Aeluros will demonstrate the following functionality of it's 10G PHY product portfolio at the OFC/NFOEC Exposition in Anaheim, CA on 7-9th March, 2006:
o EDC/LRM application: equalization of stressed input pulses in the AEL1003 device
o WAN Interface Sublayer functionality: WIS performance and clocking synthesizers on the AEL1004 device
o 10GbE NIC application: Aeluros' LAN PHY in a high performance, low cost 10G NIC environment
o Integrated VCSEL driver PHY: low cost optical module solutions for X2/XPAK/XENPAK modules
About Aeluros
Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. Aeluros' list of firsts includes:
o 1st 10G PHY/SerDes (XAUI) with <1W power consumption
o 1st LAN/WAN/FC 10G PHY capable of operating with a single external (VC)XO
o 1st 10G PHY/SerDes (XAUI) to incorporate a VCSEL driver
o 1st 10G PHY/SerDes (XAUI) with integrated EDC (10GBASE-LRM)
For more information about Aeluros, please visit the company's web site at www.aeluros.com.
CONTACT: Siddharth Sheth of Aeluros, Inc, +1-650-917-7062, or
sheth@aeluros.com
