PCI Controller features 64-bit, 33/66 MHz PCI interface.

Press Release Summary:



Providing interface between PCI bus and user interface, PCI Controller supports variety of initiator commands and functions, including configurations read/write; memory read/write, memory read multiple and memory read line; I/O read/write; parity generation and parity error detection. PCI core interface is processor independent, enabling transition to future processor generations. PCI Controller is suited for desktop and departmental servers as well as graphics and multimedia applications.



Original Press Release:



PCI Controller IP Core from iWave Systems



PCI Controller provides an interface between the PCI bus and user interface. PCI core interface is processor independent, enabling an efficient transition to future processor generations and use with multiple processors.



Highlights

• Compliant with PCI Specification 2.3

• Separate initiator and target functional blocks.



Benefits

• Core enables concurrent operation of the local bus with the processor/memory sub system

• 64-bit extension doubles the bus bandwidth



Features

•  64-bit, 33/66MHz PCI interface.

• Supported initiator commands and functions:

- Configurations read / write.

- Memory read / write, memory read multiple, memory read line.

- I/O read / write.

- Interrupt acknowledge, special cycles.

- Parity generation, parity error detection.

- Master abort.

• Parity generation, parity error detection.

• Supports a very generic user interface

• Supported target commands and functions

- Type 0 configuration space header.

- Up to six base address registers.

- Memory read / write, memory read multiple, memory read line.

- Target abort, target retry, target disconnect

- I/O read / write.

- Medium speed DEVSEL timing.

- Interrupt acknowledge.

• PCI Configuration base registers are configurable from  header file



Target Applications

•  Desktop and Departmental Servers

• Graphics and Multi-media Application



Deliverables

• Design Document

• Verilog RTL or Netlist Source code

• Test Bench

• IP User Guide



http://www.iwavesystems.com/product/fpga-ip-cores/interface-cores/pci-controller/pci-controller.html


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