Press Release Summary:
- Ideal for UMC 28nm SoC Designs and can be integrated with proprietary NAND flash controllers through a simplified version of the standard DDR DFI Interface
- PHY IP DFE contains data buffering FIFO and ONFI I/O data synchronizing Flops, DLL clocks phase selection logic and BIST
- PHY AFE contains ONFI 4.1 IO PADS, retention mode, analog DLL and DLL clock frequency
Original Press Release:
Arasan Announces NAND Flash Controller PHY and I/O Pad IP Compliant to ONFI 4.1 Specifications for UMC 28nm SoC Designs
Arasan Chip Systems expands its storage IP Portfolio with ONFI 4.1 PHY and I/O PAD IP seamlessly integrated with its NAND Flash Controller IP for UMC 28nm SoC Designs.
SAN JOSE, CALIF. (PRWEB) AUGUST 19, 2019 - Arasan today announced the immediate availability of its NAND Flash Controller PHY and I/O Pad IP for 1UMC 28nm SoC designs compliant to the latest ONFI 4.1 Specifications. The PHY IP is also backward compatible with ONFI 4.0 and 3.2 specifications. In addition to Arasan’s own NAND Flash IP Controller, the ONFI NAND PHY and I/O Pad IP can also be easily integrated with customers proprietary NAND Flash Controllers through a simplified version of the standard DDR DFI Interface. Arasan NAND Flash Controller IP is a very mature product proven on multiple customer SoC’s and built into some Xilinx FPGA’s.
Our NAND Flash PHY IP supports 1.2v and 1.8v out of the box. 2.5v and 3.3v are optionally supported on customer request.
The ACS ONFI 4.1 PHY IP consists of two major sections DFE and an AFE. The ACS ONFI 4.1 PHY IP DFE Contains:
The interface to Arasan’s NAND Flash Host Controller IP supporting ONFI 4.1 data rates
- Includes the Input / Output flops to support both NV_DDR and NV_DDR2, NV_DDR3 operation on the Data Lines.
- Includes the DLL clocks phase selection logic.
- Includes data buffering FIFO and ONFI I/O data synchronizing Flops.
- Includes Scan Logic.
- Includes BIST to perform self-test and function verification.
The ACS ONFI 4.0 PHY AFE contains:
- ONFI 4.1 IO PADS with integrated ESD protection.
- CALIO PAD to automatically calibrate the source and sink impedance of ONFI I/O and On Die termination resistors.
- Retention mode to allow VCORE power down in sleep mode.
- Analog DLL to provide the following functionality
- Generates 8 phases equally spaced of TX clock for Tuning to support various hold requirements on the ONFI DATA lines at various mode of operation.
- Generates 8 phases equally spaced of DQS STROBE clock for Tuning function of clocking the incoming data on ONFI IO.
- The DLL clock frequency can be programmed to support any constant clock frequency in the range of 20MHz to 600MHz.
The ONFI 4.1 Specification extends NV-DDR3 I/O speeds to 1066 MT/s and 1200MT/s. For better signaling performance, ONFI 4.1 adds Duty Cycle Correction (DCC), Read and Write Training for speeds greater than 800MT/s, support for lower pin cap devices with 37.5 Ohms default output resistance, and devices which require data burst exit and restart for long data input and output pauses. For lower power, 2.5V Vcc support is added. ONFI 4.1 also includes errata to the ONFI 4.0 specification.
The ONFI 4.1 NAND Flash PHY and I/O PAD IP are available immediately for 12nm, 16nm and 28nm SoC Designs. Multiple foundries are supported.
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile, automobile and drone SoC’s. We offer a comprehensive portfolio of IP for Mobile storage with JEDEC eMMC, ONFI and NAND IP for embedded storage and SD Card for removable storage. Arasan’s high-quality, silicon-proven, Total IP Solutions include Digital IP Cores, Analog PHY IP Cores, Verification IP, HDK, Software and IP Customization Services. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
Dr. Sam Beal
Arasan Chip Systems, Inc.