NEC and NEC Electronics Introduce New 45nm-node LSI Interconnect Technology for Reliability and Low-Power Consumption
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Quality Improvement of Next-Generation ULSI Based on Molecular/Atomic-Level Structure-Control Technology
TOKYO, Dec. 6 / -- NEC Corporation and NEC Electronics Corporation today announced they have developed a 45-nanometer (nm) node LSI interconnect technology that addresses both reliability and low- power consumption. The achievements are based on the reliability improvement by a low-oxygen-content (LOC) copper alloy through a special oxygen absorption process, and the power consumption savings attained by dramatically thinned, dual-damascene (DD) structures (*2) in new molecular-pore-stacked (MPS) low-k films (*1).
Features of the new technology:
(1) An LOC Cu-alloy conductor was utilized during a metal alloy step as an absorber of oxygen atoms from CU interconnects by physio-chemical reaction, and then removing the absorber layer, ensuring reliability of the fully-scaled down interconnects equivalent to that of the 65nm generation.
(2) Intensively-thinned, DD structures with MPS low-k film reduces power consumption, or essentially the parasitic capacitance of interconnects, suppressing interconnect parasitic-capacitance to the lowest levels in the world. Interconnect power consumption was decreased 24 percent compared to the 65nm node with the thorough elimination of futile power consumption.
(3) Dielectric reliability among the tiny-spaced lines was kept equivalent to that of the former 65nm-node with the low-damage etching process for the low-k material, and the side-wall protection of the line-trenches with ultra-thin polymer film.
These series of material-structure-control innovations developed by NEC and NEC Electronics based on the atomic/molecular-level, can help enable the development of advanced applications such as high-speed network servers and multi-function mobile terminals with low-power consumption.
Although LSI devices for digital consumer applications have particularly sensitive low-power consumption and high reliability requirements, device scaling narrows the interconnect spacing to increase the parasitic capacitance, or power consumption, and degrades the product yields originated from the interconnect failures. To reduce the power consumption of interconnects, two aspects are crucial: (1) the introduction of dielectric materials, such as low-k films, that store minimal charges, and (2) the minimization of the charge store area between the lines by reduction of the line height.
NEC, in collaboration with NEC Electronics and the MIRAI project, developed a MPS low-k film (k=2.4), which can easily be deposited by high vacuum simply by adjusting the deposition time period. The DD structure in the thin MPS films reduced the parasitic capacitance of interconnects by 24 percent as compared to that of 65nm nodes, achieving the world's lowest level for parasitic capacitance between 70nm-spaced lines, or essentially the minimum power consumption of interconnects.
When the cross-section of interconnects is shrunk, the probability of the open failures in the thin Cu lines is increased by mechanical and electrical stresses. The Cu interconnects consist of polycrystalline structure with many small grains, whose boundaries are potential open failure sites. The companies' research indicated that the metal oxide in the Cu interconnects also induces the open failures. To overcome these issues, the LOC Cu-alloy was innovated by the oxygen absorption process, in which ultra-thin, oxygen absorber metal of oxidizing is used more preferentially than Cu, and a Ta- barrier is put on the Cu film with Ta-barrier, the oxygen atoms on/in the Cu are absorbed by physicochemical reaction.
By the low-damage etching process and the side-wall protection of thin plasma-polymerized polymer film, the dielectric reliability of the narrow- pitched, 45nm-node interconnects was confirmed as to be equivalent to that of 65nm-nodes.
The combination of this interconnect technology and high performance 45nm- node CMOS transistors is estimated to realize a 50 percent reduction of the chip size with more than 20 percent reduction in power consumption than those of the 65nm-nodes.
NEC and NEC Electronics will continue to develop the Cu interconnect module technology with the MPS low-k film for the early mass-production of the 45nm-node low-power-consumption devices. The two companies presented the 45nm- node interconnect technology on December 5 at the International Electron Devices Meeting (IEDM), running December 5 to 7 in Washington D.C.
(*1) A deposition technology for porous low-k film that stacks the monomers with molecular-pore. This technology, which had been developed by NEC and MIRAI project jointly, was presented at the Symposium on VLSI Technology, June 2005, in Kyoto, Japan.
(*2) An interconnect structure, in which Cu film is plugged in the line trenches and the via-holes simultaneously.
About NEC Electronics
NEC Electronics Corporation specializes in semiconductor products encompassing advanced technology solutions for the high-end computing and broadband networking markets, system solutions for the mobile handsets, PC peripherals, automotive and digital consumer markets, and platform solutions for a wide range of customer applications. NEC Electronics Corporation has 26 subsidiaries worldwide including NEC Electronics America, Inc. and NEC Electronics (Europe) GmbH. Additional information about NEC Electronics worldwide can be found at www.necel.com.
About NEC Corporation
NEC Corporation (NASDAQ:NIPNY) (FTSE: 6701q.l) is one of the world's leading providers of Internet, broadband network and enterprise business solutions dedicated to meeting the specialized needs of its diverse and global base of customers. Ranked as one of the world's top patent-producing companies, NEC delivers tailored solutions in the key fields of computer, networking and electron devices, by integrating its technical strengths in IT and networks, and by providing advanced semiconductor solutions through NEC Electronics Corporation. The NEC Group employs more than 140,000 people worldwide and had net sales of 4,855 billion yen (approx. $45.4 billion) in the fiscal year ended March 2005. For additional information, visit the NEC home page at: www.nec.com/ .
* Newsroom: http://www.nec.co.jp/press/en/
CONTACT: Japan, Diane Foley of NEC Corporation, +81-3-3798-6511, or d-foley@ax.jp.nec.com; or Sophie Yamamoto of NEC Electronics Corporation, +81 44-435-1676, or sophie.yamamoto@necel.com
