Multi-Layer Interconnect is designed for 32 nm-node LSIs.
Share:
Press Release Summary:
Featuring 100 nm pitch (50 nm for both metal-width and spacings), 32 nm-node Cu multi-layer interconnect offers parasitic capacitance of 83 fF/mm. Density-modulated low-k film technology, based on plasma copolymerization technique, enables continuous alteration of dielectric constant and mechanical strength of low-k films during growth by changing supply ratio of 2 types of precursors. This achieves sequential and selective formation of porous and rigid low-k films.
Original Press Release:
NEC and NEC Electronics Develop World's First 32nm-Node Multi-Layer Interconnect
Novel Low-k Dielectric Technology Realizes Excellent Performance and High Reliability
TOKYO, Dec. 11 - NEC Corporation and NEC Electronics Corporation today announced that they have successfully developed the world's first multi-layer interconnect for 32nm-node LSIs. The joint research verified the excellent performance and high reliability of the new interconnect, owing to a newly developed low-k dielectric technology based on a plasma co-polymerization technique.
In advanced LSIs, the number of interconnects between transistors increases, while the amount of space between interconnects decreases due to miniaturization. This trend leads to higher inter-line parasitic capacitance (note 1), which may cause longer signal delays.
The introduction of porous low-k dielectrics such as molecular pore stacking film (note 2) is one solution to minimizing parasitic capacitance. However, existing porous low-k technologies cannot provide sufficient mechanical strength and insulation reliability at the 32nm-node and beyond. NEC and NEC Electronics have developed a technology that overcomes these issues, while simultaneously ensuring the high performance and low power consumption needed for next generation network servers and mobile terminals.
Features of the new technology
1. Development of a new density-modulated low-k film technology based on a plasma co-polymerization technique (note 3). The new technology enables continuous alteration of both the dielectric constant and mechanical strength of low-k films during growth by changing the supply ratio of two types of precursors - one for forming porous film and the other for harder dielectric film - without breaking the vacuum. This achieves sequential and selective formation of porous and rigid low-k films, for which high mechanical robustness and adhesion strength have been confirmed.
2. Development of a high-precision, selective, dry-etching technology for fine-patterning the density-modulated low-k film.
3. Fabrication of a 32nm-node Cu multi-layer interconnect with 100nm pitch (i.e. 50nm for both metal-width and spacings) utilizing the aforementioned technologies, enabling a dramatic improvement in insulation reliability (leakage current is suppressed by three orders of magnitude as compared with conventional technology) with a low parasitic capacitance (83fF/mm), confirming high-speed and low-power consumption benefits.
As the integration density of Si LSI devices increases, the number of interconnects increases, resulting in higher parasitic capacitance and undesirable power consumption levels. One approach to decreasing parasitic capacitance is the introduction of low-k films such as organic silica films (SiOCH) with low polarizability, which have already been introduced in 90nm- node LSIs. Porous low-k films (obtained by introducing pores into low-k films) have been investigated for 65nm-node LSIs to further decrease capacitance. By further advancing low-k material technology, NEC, in collaboration with the MIRAI project, developed a molecular-pore-stack (MPS) low-k film, in which sub-nanometer pores were introduced uniformly. This film was then successfully applied to 45nm-node LSI interconnects.
However, there was still a challenge that needed to be addressed before 32nm-node interconnects could be realized. In general, porous low-k films are effective in decreasing parasitic capacitance, but their mechanical strength tends to decline as the porosity increases. Therefore, porous low-k films are usually used in combination with films possessing high mechanical strength. With conventional technology, these films are deposited with different processing tools, but changing tools while the film is grown inevitably exposes the wafer surface to the air, causing residual defects between each film, and giving rise to nonideality in the insulation property.
NEC and NEC Electronics' new technology achieves consecutive formation of different types of films in a single step, with a single tool, without breaking the vacuum. The density modulation technology for low-k films enables control of dielectric constants and mechanical strength of low-k films by changing the mixing ratio of two types of precursors using plasma co- polymerization technology. This single-step deposition prevents creation of defects at the interface between films, resulting in a decrease in leakage current by three orders of magnitude as compared with conventional interconnects. Moreover, the mechanical strength of the new film is twice as strong as that of conventional film, while maintaining an equal dielectric constant. Simultaneously, a novel, selective, dry-etching technique with enhanced precision was developed. This technique allows sensitive detection of the density modulation of low-k films.
By combining the above achievements, a highly reliable low-k interconnect structure was realized that does not incur current leakage, despite miniaturization of the patterning dimensions down to 50nm for 32nm-node LSIs. Moreover, interline capacitance of 83fF/mm was accomplished; a level in line with that previously achieved for 45nm-node interconnects, proving successful in suppressing power consumption. In 32nm-node ULSI interconnects, integration density is equivalent to that of placing a maximum of ten thousand lines within 1mm-width.
NEC believes that interconnect module technology using density-modulated low-k technology is essential to realizing 32nm-node ULSIs, and it will continue to advance its research activities toward their early realization.
This research result has been realized by advancing technologies developed in the first and second stages of the MIRAI project "Interconnect Module Technology with Low-k Materials" (note 4) and through joint research carried out by NEC and MIRAI. The organic silica precursors used in the research were supplied by Tosoh Corporation and Tosoh Finechem Corporation. NEC and NEC Electronics will present the results of this research at the International Electron Devices Meeting (IEDM) 2006, being held from December 11 - 13 in San Francisco, USA.
Notes:
1. In large-scale integrated interconnects, the presence of neighboring metal lines is equivalent to having capacitor devices placed unintentionally, causing an effect called parasitic capacitance. When the parasitic capacitance of an interconnect is large, the signal is delayed, therefore increasing power consumption due to excess charging and discharging of electricity during signal propagation.
2. A new-concept low-k film that is deposited in the vacuum by stacking silica-based precursor molecules, whose molecular structure is designed to contain a molecular pore. Low-k film with a dielectric constant of 2.4 was realized for 45nm-node LSIs through piling of a "molecular ring chain," consisting of 3 silicon atoms and 3 oxygen atoms that are activated in plasma. This is the result of an NEC and MIRAI joint research project.
3. A technology for depositing new films in a vacuum by introducing two types of precursors into plasma using co-polymerization reaction. This technology was basically demonstrated by the MIRAI project for organic dielectrics and was presented at the International Electron Devices Meeting (IEDM) 2003. A new plasma-enhanced co-polymerization (PCP) technology for reinforcing mechanical properties of organic silica low-k/Cu interconnects on 300 mm wafers Kawahara, J.; Nakano, A.; Kunimi, N.; Kinoshita, K.; Hayashi, Y.; Ishikawa, A.; Seino, Y.; Ogata, T.; Takahashi, H.; Sonoda, Y.; Yoshino, T.; Goto, T.; Takada, S.; Ichikawa, R.; Miyoshi, H.; Matsuo, H.; Adachi, S.; Kikkawa, T.; International Electron Devices Meeting, 2003. IEDM '03 Technical Digest, IEEE International8-10 Dec. 2003 Page(s):6.2.1 - 6.2.4
4. The first stage of the MIRAI project "Interconnect Module Technology with Low-k Materials" was carried out from July 2001 to March 2004, and the second stage from April 2004 to March 2006. NEC participated in the project. MIRAI projects are supported by the New Energy and Industrial Technology Organization ("NEDO").
About NEC Corporation
NEC Corporation (NASDAQ:NIPNY) is one of the world's leading providers of Internet, broadband network and enterprise business solutions dedicated to meeting the specialized needs of its diverse and global base of customers. NEC delivers tailored solutions in the key fields of computer, networking and electron devices, by integrating its technical strengths in IT and Networks, and by providing advanced semiconductor solutions through NEC Electronics Corporation. The NEC Group employs more than 150,000 people worldwide. For additional information, please visit the NEC home page at: www.nec.com/ .
About NEC Electronics Corporation
NEC Electronics Corporation specializes in semiconductor products encompassing advanced technology solutions for the high-end computing and broadband networking markets, system solutions for the mobile handset, PC peripherals, automotive and digital consumer markets, and platform solutions for a wide range of customer applications. NEC Electronics Corporation has 24 subsidiaries worldwide including NEC Electronics America, Inc. ( www.am.necel.com/ ) and NEC Electronics (Europe) GmbH ( www.eu.necel.com/ ). For additional information about NEC Electronics worldwide, visit www.necel.com/ .
