Press Release Summary:
MIPI subsystem, consisting of Camera Serial Interface (CSI-2) and Low-Voltage Differential Signaling (LVDS) in UMC's 40 nm LP process, also includes Co-IP (Composite IP), prototype, and system loopback testing. Co-IP integrates combo PHY IP, MIPI CSI-2 RX controller, and LDVS controller and is configurable for various sensor interfaces to support transmission speeds to 1 Gbps for each of 4 data lanes. Prototype (combo PHY EVB and controller FPGA code) helps advance designs to pre-silicon stage.
Original Press Release:
Faraday Announces Its Silicon-Proven MIPI Subsystem to Enable Faster Time-to-Market
Consisting of CSI-2 RX, LVDS, and Combo PHY IP in 40nm LP, and Prototype, the subsystem has been adopted widely in the market
HSINCHU -- Faraday Technology Corporation (TWSE: 3035), the leading fabless ASIC/SoC and IP provider, today announced the availability of its MIPI subsystem of Camera Serial Interface (CSI-2) and Low-Voltage Differential Signaling (LVDS) in UMC's 40nm LP process. The system-level solution perfectly meets both the requirements of quality and cost within the competitive schedule for applications of IoT, mobiles, and cameras, such as wearable and mobile devices, Digital Still Camera (DSC), surveillance, automotive and medical devices.
Faraday's MIPI subsystem includes Co-IP (Composite IP), the prototype, and system loopback testing. The silicon-proven Co-IP integrates combo PHY IP, MIPI CSI-2 RX controller, and LDVS controller. It is configurable for various sensor interfaces of MIPI, LVDS, sub-LVDS, and HiSPi, supporting the transmission speed up to 1Gbps for each of 4 data lanes. The prototype (combo PHY EVB and controller FPGA code) assists customers in creating their platforms and bringing system-level development and verification forward to the pre-silicon stage. In addition, the at-speed system loopback testing ensures mass production quality at a lower cost.
"Faraday has upgraded its IP offering to the system level to meet the rapid market needs," said Jason Hung, Vice President of R&D at Faraday. "We are proud to provide the pre-valid MIPI subsystem with high interoperability. It not only effectively lessens the integration efforts and risks in SoC implementation but also advances system-level development to shorten the design cycle time with guaranteed SoC performance and quality," he added.
"Through close collaboration with lead-edge SoC customers, we saw increasing MIPI adoption in various applications beyond the mobile market," said Jensen Yen, associate vice president of marketing and spokesperson at Faraday Technology. "Faraday's flexible MIPI subsystem can accelerate customers' product creations to satisfy differential requirements in the market. It has been adopted by some of our customers in the multimedia field and enabled quicker tape-outs than they expected, including a leading surveillance vendor. In addition to MIPI, Faraday will continue development in other IP subsystems for more application fields," he added.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, MPEG4, H.264, USB 2.0/3.0, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes (10Gbps), etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and mainland China. Faraday is listed on the Taiwan Stock Exchange, ticker 3035. For more information, please visit: www.faraday-tech.com.
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